Current Cartilage Entry Points
Current mechanism packageCartilage Core: Reconfigurable Fabric in WebGL and SystemVerilog
The public source repository publishes the compact WebGL1 model, editable hardware paper and PDF, local-clocked SystemVerilog RTL, and self-checking Verilator testbench. The checked 6x6 image receives 252 payload bits plus one apply pulse and settles to an interior-MUX AND circuit.
Evidence boundary: logical mechanism and one exact installed image, not silicon signoff or a general placer/router.
Cartilage 2026: Child-Owned Reconfiguration Ports: the earlier WebGL/GPGPU visual milestone for child-owned reconfiguration port roots, square 6x6 ownership blocks, active port-root initialization, and the 450-frame capture.
Cartilage Visual Language: the 32-code body-role alphabet for reconfiguration ports, crosses, constants, wires, and MUX modes.
Cartilage Nested-Instantiation Demo: the canonical browser/GPU demo for local ports, bounded daughter regions, serial configuration streams, and visible nested replacement.
Hardware And Signal Artifacts
One-Pin FPGA FM Receiver: How Much Radio Do You Actually Need?: a one-pin FPGA radio article with a preserved Verilog follow-up and explicit limits.
Bit-serial bubbles-free multiplier: a positive-number Logisim circuit artifact focused on regular serial scheduling.
Open Research Boundaries
Cartilage Run and Sketch Index collects the Cartilage run, timeline, and sketch pages in one place.
Wafer-Diced Chiplets for Programmable Matter and Claytronics connects protected chiplets, near-field links, and spatial computation to the old Claytronics problem.
LinkedIn publication index keeps dated source posts available beside the fuller project pages.