Choose a mechanism and enter where it works: at the pin, packet, clock, shader pass, circuit tile, or reconfiguration bit.
These systems rebuild parts of computing that inherited stacks usually hide. Synthesize 106 independently moving RF channels through one FPGA pin, stream a 64-bit product or binary32 quotient through one-bit arithmetic, send an FPGA image through Ethernet, compose logic by hand, or install a circuit into a live spatial fabric.
The multiplier and divider add open-source RTL, rebuild scripts, utilization reports, exact oracles, and physical run data to the measurements, photographs, videos, and runnable machines available here.
Arithmetic scheduling
The multiplier accepts a new operand word every 64 clocks at 216 MHz and delivers 3.375 million low 64-bit products per second from 254 LUT4s and 635 flip-flops.
Twelve cores fit the HX8K for 40.5 million products per second. Download the open RTL, FPGA build, utilization report, host verifier, and physical results.
Correctly rounded binary32
The divider accepts raw binary32 operands LSB first, computes through one-bit significand, exponent, and sign streams, and begins another finite-normal division every 32 clocks at 216 MHz.
The physical HX8K run returned the correct quotient in all 65,536 cases. Download the open RTL, rebuild scripts, exact integer oracle, utilization report, bitstream, and run data.
Browser GPU systems
Raw WebGL1 and GLSL ES 1.00 turn packed texture state, framebuffer passes, ping-pong updates, and readback into working cellular automata and reconfigurable fabrics.
The browser becomes a spatial-computing machine: every shader pass advances a field of local state transitions in parallel.
Reconfigurable computation
The path begins with Logisim and LUTs, then builds through CMOS gain, output drivers, clock and event distribution, state machines, timing, metal routing, nested components, and runtime reconfiguration in space.
Each chapter connects one layer of the machine to the next, from physical switching to a live fabric that installs new circuitry while it runs.
The FPGA systems map joins radio, arithmetic, Ethernet, reconfiguration, and source into one engineering path.
To build the foundations behind these systems, learn FPGA and Verilog from first principles: Boolean logic through simulation, synthesis, place-and-route, and a programmed iCE40 board.
RF transmit ยท complete source
One HX8K synthesizes 106 independently phased and deterministically modulated FM lanes, adds them through twin bit-serial I/Q trees, converts the composite to one-bit density streams, and selects the complete RF result onto N16. Download every required RTL, constraint, build, hardware, license, and FPGA-image file.
RF receive
A single logical differential input site carries thresholded RF into DDR sampling, DDS-controlled one-bit mixing, integration, cross-product demodulation, and sigma-delta audio output. The operating video and selected UP5K source follow that complete receive path.
Ethernet and configuration
The 2020 multi-file source receives RMII Ethernet, answers ARP, ingests a fixed-layout FPGA image through IPv4/UDP, stores it in RAM, and configures an adjacent iCE40LP384 directly. A Linux UDP/XCB/EGL shell controls the path.
Physical-computing education
Palm-scale role variants and connector spacing turn a multiplexer into a tangible construction alphabet. Original photographs show the fabricated assemblies and manual compositions; the learning path connects those physical selectors to Logisim and FPGA LUTs.
Run Cartilage in the Browser introduces the public and private workstation paths. The open one-slot multiplier is self-contained, requires no account, and loads its routed circuit directly from the page.
Private access adds circuit editing, loading, saving, sharing, and a view into the ongoing browser, Raspberry Pi, and FPGA streaming work. Request the private demo username and password on LinkedIn.
Cartilage Core carries the same compact reconfigurable fabric through WebGL1 and local-clocked SystemVerilog RTL. The public source repository includes the browser machine, editable hardware paper and PDF, RTL, and a self-checking Verilator testbench.
A 6x6 image accepts 252 payload bits and one apply pulse, then becomes an interior-MUX AND circuit. The matched implementations make spatial reconfiguration concrete at both the shader and RTL levels.
Runtime Instantiation in Space sends a serial configuration stream from a local parent port into a daughter region. Cartilage Visual Language defines the body-role alphabet that makes those regions readable.
The Cartilage roadmap advances the renderer, region roots, ownership, recovery, simulator, hosting, and teaching system toward a practical visual workstation.
One-Pin FPGA FM Receiver compresses an FM receive chain into one FPGA input and follows the signal through the Verilog.
The Missing Maker Fab opens a manufacturing path between integrated-circuit simulation and accessible physical fabrication.
Wafer-Diced Chiplets for Programmable Matter and Claytronics joins protected chiplets, near-field links, and spatial computation into a route toward matter that computes through its structure.
Cartilage Runs And Designs collects executable machines and design studies; the ordered Cartilage learning path develops the architecture layer by layer.