The One-Chapter-At-A-Time Route
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Logisim, The MUX, And LUT1 Through LUT6
PublishedMake the selector visible, grow it into stored truth tables, then connect LUT4 to Lattice iCE40 and LUT5/LUT6 to AMD/Xilinx configurable logic.
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CMOS Inverters As Gain, Restoration, And Output Drive
PublishedMove below Boolean symbols. A real inverter has a voltage-transfer curve, gain through its transition region, noise margins, finite output current, and capacitive load. Logic survives a long computation because stages restore levels and sized drivers supply fanout.
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Clock, Event, And Reset Trees; H-Trees And Driver Grids
PublishedA high-fanout event is a physical distribution problem. Buffer trees, H-shaped geometry, grids, and segmented regional networks trade skew, insertion delay, energy, metal, and locality. Cartilage needs the same question for configuration edges and application events, not only for a conventional global clock.
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Harel Statecharts And One-Hot Spatial State Machines
PublishedHarel statecharts add hierarchy, concurrency, and event-driven transitions to flat finite-state diagrams. A one-hot encoding gives each state a visible storage location. Together they provide a bridge from behavioral composition to a machine whose active state occupies space.
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Clock Regions And Timing Closure
PublishedPlacement decides path length; fanout requires buffers; congestion detours routes; clocks cross region boundaries; and final routed delays must satisfy setup and hold constraints. This is where a logical architecture meets a realizable device.
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Metal Wires Are Part Of The Machine
PublishedWires are not free arrows. Layers, vias, resistance, capacitance, direction, and routing capacity determine what a connection costs. Cartilage side-metals make locality visible while remaining distinct from physical IC closure.
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OOP-Style Nested Components And Composition
PublishedA component owns state and an interface; a parent composes children without flattening their identity. Cartilage turns that software intuition into spatial ownership: the child is a bounded region, the interface is a local boundary, and the configuration path is represented inside the fabric.
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Runtime Instantiation In An Adjacent Region
Artifact wrapperA parent uses a local reconfiguration port to stream a complete image into a neighboring daughter region. The daughter can receive new wire, intersection, constant, MUX, or port roles. That bounded replacement is the concrete example of dynamic reactivity on space.
Source Anchors For The Teaching Path
These are not decorative “further reading” links. Each one anchors a specific step in the path to a maintained tool, a device manual, a primary paper, or a physical-design reference.
Logisim-evolution
The maintained cross-platform logic design and simulation tool. The public multiplier artifact itself remains in legacy Logisim 2.7.1 format.
Lattice iCE40 Technology Library
The official SB_LUT4 primitive and its 16-bit LUT_INIT address mapping.
AMD UltraScale CLB Guide
The official 6-input LUT and dual-LUT5 modes, with storage, carry, routing, and slice context.
MIT: Inverter Basics
CMOS, transfer characteristics, noise margins, and sizing—the physical basis for treating an inverter as a restoring gain stage.
AMD UltraScale Clock Structure
Clock regions, horizontal spines, vertical and horizontal tracks, roots, leaf buffers, and segmented regional distribution.
Harel's Statecharts Paper
The 1987 primary paper introducing a visual formalism for complex systems with hierarchy, orthogonality, and event-driven behavior.
AMD Timing-Closure Methodology
Constraints, clocking, congestion, path delay, skew, and the iterative work required to make a placed and routed design meet timing.
OpenROAD Parasitics Estimation
Routing-layer resistance and capacitance, clock-versus-signal wire models, and delay estimation after placement or global routing.
After The Foundations: Use The Evidence In This Order
Cartilage Visual Language
Decode reconfiguration ports, crosses, constants, wire orientations, and the MUX modes before judging a fabric render.
Nested Instantiation
The canonical wrapper for the local-port, daughter-region, and bounded replacement idea.
Cartilage Core
The compact WebGL1 model, hardware paper, SystemVerilog RTL, Verilator testbench, and one exact 252-bit installation.
6 + 5 Full-Frame Run
A seeded 3-bit ripple-carry adder body, 256 updates, 257 captured states, source, manifests, and run reports.
Use the Cartilage run and sketch index only when you need the wider record of checked runs, timelines, sketches, and debug fixtures.
What Will Not Be Repeated
The older self-contained WebGL files remain preserved artifacts. They will not be mechanically rewritten just to acquire modern site chrome. The old AI-assisted simulator pages also do not define the teaching sequence. Pages with overlapping labels, weak explanatory copy, or ambiguous proof claims belong in the run-and-sketch record, below this reader path.
New chapters should be published only when they have a clear construction, an attributable diagram or inspectable artifact, primary links, and one deliberate next step. That is slower than generating six simulators at once. It is also how Cartilage becomes teachable.