Build The Cartilage Spatial Circuit Workstation: A 28-Part Roadmap

A defining block attaches a stable non-reconfigurable component tag to every cell in its subtree. The tag supplies display and authoring metadata while the continuous ownership tree and its writer authority remain unchanged. From tag membership, the renderer derives block backgrounds, exact contours, hover and focus states, labels, and inspection data.

A continuous-line mode turns each unbranched net into one readable route. Static arrowheads show direction during pause, print, and reduced motion; optional slow interframes expose the modeled propagation order. Selecting any segment reveals the complete named net, its single driver, every branch and sink, and each component contour it crosses.

• ERG-01Tag exact component subtrees. Let a defining block name every member cell while the enclosing ownership tree continues through it.Planned

  Completion test: Stable membership survives placement and simulation, and every parent chain retains its original path.

• ERG-02Select blocks by mouse, keyboard, or touch. Give every tagged component a distinct background, hover, focus, and selection treatment.Planned

  Completion test: Selection reveals the block name, cells, ports, and runtime state while every signal remains visible.

• ERG-03Draw exact component contours. Follow every change in adjacent cell tags through concave and nested shapes.Planned

  Completion test: Adjacent blocks share one readable seam, and nested blocks keep distinct hit targets.

• ERG-04Render unbranched wires as continuous routes. Keep crossings, junctions, MUXes, and values distinct at every zoom.Planned

  Completion test: One route remains legible in overview and close inspection with no cell-by-cell bubble chain.

• ERG-05Animate modeled propagation order. Tie optional slow interframes to real engine steps and retain static arrows for pause, print, and reduced motion.Planned

  Completion test: One recorded step sequence produces the same visible order on every replay and labels that order as modeled time.

• ERG-06Trace fanout from any segment or port. Highlight the full connected net across branches and component regions.Planned

  Completion test: A one-driver, three-sink circuit identifies exactly those endpoints and excludes a crossing with no junction.

• ERG-07Name every net and port. Preserve wire labels and distinguish input, output, and configuration ports through shape, text, and color.Planned

  Completion test: Labels clear the fabric marks, follow rerouted nets, and survive save and reload.

One logical root can occupy several physical cells or lanes while presenting independent configuration clock, data-in, data-out, and ownership-tree channels. Measurement across supported orientations will determine the minimum footprint; the 2×2 diagram supplies the first candidate geometry.

The reviewed transition rotates a cell’s parent direction while it searches for a live configuration signal. The roadmap replaces open-ended search with an explicit claimable power-on image and an ordered spanning-tree wavefront whose edge arbitration and child order produce the same region on every run.

• ROOT-01Build the multi-cell root interface. Give one contiguous logical root named clock, data-in, data-out, and tree connections.Planned

  Completion test: Every channel drives and reads independently through all supported orientations.

• ROOT-02Install an explicit power-on claim state. Initialize every unclaimed cell with a defined reconfiguration role and deterministic discovery behavior.Planned

  Completion test: Repeated full resets produce one state hash, and every cell exits parent search.

• ROOT-03Claim regions through an ordered spanning tree. Specify edge arbitration, parent rotation, fixed child order, and the closing wavefront.Planned

  Completion test: Every parent chain reaches one root, each cell appears once, and repeated runs emit one visit order.

• ROOT-04Claim, configure, and read a whole region. Extend beyond the root footprint through all three configuration channels.Planned

  Completion test: One trace records the claim, deterministic load, returned output, and every cell attached to the root.

Ownership overlap places logical containment and shared application references above a physical ownership forest. In the 4×4 circuit, every non-root cell keeps exactly one adjacent parent, while exactly one surrounding block holds the current writer capability.

A passable ownership pointer moves that unique mutation authority through an ordered handoff: fence the old writer, acknowledge the new generation, reject stale pointers, and release the old capability.

physical parents per non-root cell = 1
active writers per mutable shared object ≤ 1
writer transfer = fence → acknowledge → generation change → release

• OWN-01Overlay sharing on the physical parent forest. Represent overlapping logical blocks and references while each cell keeps one physical parent edge.Planned

  Completion test: The inspector displays both graphs, and every physical parent walk reaches exactly one root.

• OWN-02Enforce one writer capability. Serialize conflicting commits for every mutable shared object.Planned

  Completion test: Exactly one of two competing writes commits, and the object rejects every stale generation.

• OWN-03Transfer writer authority atomically. Fence, acknowledge, advance the generation, and release while preserving the stored object.Planned

  Completion test: Exactly one writer exists before and after the handoff, and every interrupted step follows a deterministic recovery path.

• OWN-04Run the 4×4 shared-object circuit. Surround one subfabric with four blocks and pass the writer among them.Planned

  Completion test: The traversal visits all 16 cells once, reader removal and writer transfer preserve the object, and the overlay names every relationship.

The roadmap’s sequential serial kill pill travels as a bounded reset token rather than a global clear. One surrounding owner can establish and inject through a complete perimeter; several surrounding owners collaborate on one ordered transaction.

The token traverses the perimeter and returns to its injection point before it authorizes the enclosed reset. The subfabric then receives the same explicit claimable image as power-on. Open, branched, duplicated, or incomplete contours abort the transaction before any cell changes.

• REC-01Identify a recoverable stuck island. Detect a self-parenting or cyclic enclosed object after external application connections leave or quiesce.Planned

  Completion test: The detector separates injected stuck circuits from live transactions that continue to make progress.

• REC-02Encode the serial recovery token. Specify its start, direction, generation, duplicate handling, acknowledgement, and timeout states.Planned

  Completion test: Ordinary configuration traffic and stale generations never initiate a reset.

• REC-03Construct one closed contour. Give every boundary member exactly one predecessor and one successor along the shortest valid perimeter.Planned

  Completion test: The token visits each perimeter segment once, while open and branched contours stop before reset.

• REC-04Coordinate every surrounding owner. Unify single-owner and multi-owner perimeters into one recovery generation.Planned

  Completion test: One-, two-, and four-participant circuits agree on one generation or stop with every enclosed cell unchanged.

• REC-05Close the loop and restore power-on state. Let the returning token reset the enclosed object and install its defined claimable image.Planned

  Completion test: The reset hash matches a fresh power-on instance, and every cell outside the contour retains its state.

Play, pause, single-step, and speed controls govern both engine state and propagation view. Saving keeps the editable source project distinct from an optional runtime checkpoint. Static hosting publishes the application, while an authenticated project service adds versions, permissions, quotas, and conflict-safe writes.

• SIM-01Control time directly. Add play, pause, step, reset, speed, an engine tick counter, and deterministic resume.Planned

  Completion test: Pause holds one checksum, and checkpoint replay yields the same sequence of state hashes.

• SIM-02Save and reopen complete circuits. Serialize the versioned editable project separately from an optional runtime checkpoint.Planned

  Completion test: Save-load-save preserves every block, net, port, ownership, annotation, and machine-state identity.

• SIM-03Host and share versioned projects. Connect the browser app to permissions, quotas, generations, and conflict-safe writes.Planned

  Completion test: A clean HTTPS session opens the shared project, and the service rejects unauthorized or stale writes.

• SIM-04Persist the inspection view. Store labels, colors, probes, block treatments, and net identities as project annotations beside installed cell state.Planned

  Completion test: Rerouting and reopening preserve each named object across screen-geometry changes.

Every lesson starts from a deterministic engine snapshot, triggers one visible action, and reads one machine result. The sequence begins with constants, wires, a MUX, fanout, names, and ports, then advances through state, composition, regional reconfiguration, writer transfer, and closed-contour recovery.

• LEARN-01Embed the workstation engine in every lesson. Route tutorial buttons into the same Cartilage simulator used for circuit work.Planned

  Completion test: A fresh browser runs the lesson through visible controls and the live engine.

• LEARN-02Inject signals through visible controls. Connect start, back, next, check, reset, play, and pause to named ports and nets.Planned

  Completion test: Each action produces one named state transition and one engine-state result.

• LEARN-03Teach spatial behavior beyond gates. Lead readers from selector fanout into feedback, named components, regional replacement, shared objects, writer handoff, and recovery.Planned

  Completion test: The public sequence includes dynamic regional behavior beyond conventional gate lessons.

• LEARN-04Make every lesson repeatable and accessible. Package fixed starting states, target hashes, independent reset, keyboard operation, mobile layouts, and saved progress.Planned

  Completion test: Automated playback reaches every expected checkpoint, and back or reset starts each lesson from its own state.