One Multiplexer Builds Every Two-Input Logic Gate

One selector, two constants, and two inputs generate the complete two-variable Boolean universe.

A MUX controlled by B chooses among 0, 1, A, and NOT A. Those four sources produce every Boolean function of A and B—then run as real routes in the Cartilage fabric.

One Rule Controls Every Circuit

M(S, D0, D1) = S ? D1 : D0

Each lesson connects equation to machine. The clean circuit appears first; the same function follows as a placed and routed Cartilage fabric. A pale beige square marks a MUX tile, a filled dark ring carries 1, and a hollow ring carries 0. Open any fabric image or Native link to inspect its pixels.

A 2-to-1 multiplexer with selector S equal to zero; the solid selected route connects D0 to output Y while D1 is dashed — `S=0` connects `D0` to `Y`.

Actual Cartilage GLSL fabric rendering of a 2:1 MUX selecting its D0 input when S is zero. — `S=0` connects `D0` to `Y`.

A 2-to-1 multiplexer with selector S equal to one; the solid selected route connects D1 to output Y while D0 is dashed — `S=1` connects `D1` to `Y`.

Actual Cartilage GLSL fabric rendering of a 2:1 MUX selecting its D1 input when S is one. — `S=1` connects `D1` to `Y`.

The selector connects exactly one input path to the output. Composition turns that controlled connection into logic.

Four Sources Cover Every Behavior Of A

With A as the only live input, an output can equal 0, A, 1, or NOT A. The same MUX geometry creates all four, and a two-bit pointer names each source.

Pointer 00 represented by a multiplexer selected by A with both data inputs tied to zero, producing constant zero — `00`: tie both data inputs to zero. The result is always `0`.

Actual Cartilage GLSL fabric rendering of a MUX producing zero for both values of A. — `00`: tie both data inputs to zero. The result is always `0`.

Pointer 01 represented by a multiplexer selected by A with D0 tied to zero and D1 tied to one, producing A — `01`: choose between zero and one with `A`. The result follows `A`.

Actual Cartilage GLSL fabric rendering of a MUX following A. — `01`: choose between zero and one with `A`. The result follows `A`.

Pointer 10 represented by a multiplexer selected by A with both data inputs tied to one, producing constant one — `10`: tie both data inputs to one. The result is always `1`.

Actual Cartilage GLSL fabric rendering of a MUX producing one for both values of A. — `10`: tie both data inputs to one. The result is always `1`.

Pointer 11 represented by a multiplexer selected by A with D0 tied to one and D1 tied to zero, producing NOT A — `11`: choose the opposite constant with `A`. The result is `NOT A`.

Actual Cartilage GLSL fabric rendering of a MUX producing NOT A. — `11`: choose the opposite constant with `A`. The result is `NOT A`.

AND Emerges One Branch At A Time

Hold B constant and follow the output as A changes. Each value of B selects one of the four sources above.

AND with B fixed at zero; both values of A produce zero, so the branch selects source zero with pointer 00 — When `B=0`, AND must be zero for both values of `A`. Choose source `0`.

Actual Cartilage GLSL fabric rendering of the AND MUX branch with B zero, forcing Y to zero. — When `B=0`, AND must be zero for both values of `A`. Choose source `0`.

AND with B fixed at one; the output follows A, so the branch selects source A with pointer 01 — When `B=1`, AND follows `A`. Choose source `A`.

Actual Cartilage GLSL fabric rendering of the AND MUX branch with B one, passing A to Y. — When `B=1`, AND follows `A`. Choose source `A`.

A minimal AND circuit: one multiplexer selected by B with D0 equal to zero and D1 equal to A, plus all four truth-table outputs — `B=0` forces zero; `B=1` passes `A`. Only `A=1, B=1` produces one.

Actual Cartilage GLSL fabric rendering of AND, placed and routed as a compact one-MUX patch matching M(B,0,A). — `B=0` forces zero; `B=1` passes `A`. Only `A=1, B=1` produces one.

AND = M(B, 0, A) pointer word 00|01 = 0001

Actual Cartilage GLSL fabric frames for a one-MUX AND patch with A and B high; the signal advances through the fabric and output Y rises on cycle two — Each frame advances exactly one native GLSL fabric transition. Watch the dark `1` state enter the beige MUX tile: with `A=1` and `B=1`, `Y` rises on cycle 2. A postprocess composites labels over unscaled renderer captures.

The Construction Reaches All 16 Functions

Store the four truth bits directly

Store the outputs as C00, C10, C01, and C11. Two MUXes choose by A; a third chooses the correct column by B. Four freely chosen bits span all 16 two-input functions.

A universal LUT2 tree made from three 2-to-1 multiplexers and four stored truth bits; A selects within each B column and B selects the column — Three nested 2:1 MUXes select one of four stored truth bits. This is the direct LUT2 construction.

Actual Cartilage GLSL fabric rendering of a universal two-input lookup table using three routed MUX tiles and four programmable truth-bit leaves. — Three nested 2:1 MUXes select one of four stored truth bits. This is the direct LUT2 construction.

Store two source pointers

The 2020 construction uses another four-bit encoding. Each fixed-B column equals 0, A, 1, or NOT A, so two source addresses replace four direct truth bits.

A two-input truth table split into B equals zero and B equals one columns; each two-bit column maps to source zero, A, one, or NOT A and its manuscript pointer code — Each `B` column is one two-bit behavior of `A`, so each column needs only a two-bit source pointer.

Actual Cartilage GLSL fabric rendering of an AND truth table split into two A-selected branches and one final B-selected output. — Each `B` column is one two-bit behavior of `A`, so each column needs only a two-bit source pointer.

A four-bit configuration word split into C3 C2 for the B equals zero branch and C1 C0 for the B equals one branch — The high pair addresses the `B=0` source. The low pair addresses the `B=1` source.

Actual Cartilage GLSL fabric rendering showing the four-bit 01|11 pointer word driving the complete wide selector network for XOR. — The high pair addresses the `B=0` source. The low pair addresses the `B=1` source.

Clean block and circuit diagram of the complete source-pointer network: a bank of zero, A, one, and NOT A feeds two addressed 4-to-1 pickers and a final B-selected 2-to-1 MUX — Both addresses see the same four sources. `B` chooses which addressed branch reaches `Y`.

Actual Cartilage GLSL fabric rendering of the complete eight-MUX 2020 pointer network configured as XOR, in a wide compact 15 by 13 tile route. — Both addresses see the same four sources. `B` chooses which addressed branch reaches `Y`.

The two encodings record different things. A truth vector lists four outputs in the visible order A0B0, A0B1, A1B0, A1B1. The pointer word stores two source addresses in the order B=0 | B=1.

For example, XOR has truth vector 0110 but pointer word 01|11 = 0111.

Every Two-Input Function Becomes A Circuit

Each card shows minimal 2:1 MUX wiring, four visible truth outputs, and the pointer word. Constants and direct wires use zero MUXes. XOR, XNOR, NAND, and NOR use two; every other nontrivial function uses one.

When B=0, source 0 uses pointer 00

The high pointer pair is 00.

FALSE Boolean function tied directly to zero, with truth vector 0000 and pointer word 0000 — FALSE is a direct constant: `Y=0`.

Actual Cartilage GLSL fabric rendering of FALSE, using one zero-constant tile. — FALSE is a direct constant: `Y=0`.

AND built with one MUX selected by B, D0 equal to zero, and D1 equal to A — AND: `B=0` forces zero; `B=1` passes `A`.

Wire B connected directly to output Y, with truth vector 0101 and pointer word 0010 — WIRE B is direct: `Y=B`.

Actual Cartilage GLSL fabric rendering of WIRE B, using a direct two-tile routed wire and no logical MUX. — WIRE B is direct: `Y=B`.

B AND NOT A built with one MUX selected by A, D0 equal to B, and D1 equal to zero — `B AND NOT A`, also `B ↛ A`: `A=0` passes `B`; `A=1` forces zero.

Actual Cartilage GLSL fabric rendering of B AND NOT A, placed and routed as a compact one-MUX patch matching M(A,B,0). — `B AND NOT A`, also `B ↛ A`: `A=0` passes `B`; `A=1` forces zero.

When B=0, source A uses pointer 01

The high pointer pair is 01.

A AND NOT B built with one MUX selected by B, D0 equal to A, and D1 equal to zero — `A AND NOT B`, also `A ↛ B`: `B=0` passes `A`; `B=1` forces zero.

Actual Cartilage GLSL fabric rendering of A AND NOT B, placed and routed as a compact one-MUX patch matching M(B,A,0). — `A AND NOT B`, also `A ↛ B`: `B=0` passes `A`; `B=1` forces zero.

Wire A connected directly to output Y, with truth vector 0011 and pointer word 0101 — WIRE A is direct: `Y=A`.

Actual Cartilage GLSL fabric rendering of WIRE A, using a direct two-tile routed wire and no logical MUX. — WIRE A is direct: `Y=A`.

OR built with one MUX selected by B, D0 equal to A, and D1 equal to one — OR: `B=0` passes `A`; `B=1` forces one.

Actual Cartilage GLSL fabric rendering of OR, placed and routed as a compact one-MUX patch matching M(B,A,1). — OR: `B=0` passes `A`; `B=1` forces one.

XOR built with two MUXes: the first makes NOT A and the second, selected by B, chooses A or NOT A — XOR: first make `NOT A`; then let `B=0` pass `A` and `B=1` pass `NOT A`.

Actual Cartilage GLSL fabric rendering of XOR, placed and routed as a compact shared-A two-MUX patch. — XOR: first make `NOT A`; then let `B=0` pass `A` and `B=1` pass `NOT A`.

When B=0, source 1 uses pointer 10

The high pointer pair is 10.

NOT B built with one MUX selected by B, D0 equal to one, and D1 equal to zero — NOT B: `B` chooses the opposite constant.

Actual Cartilage GLSL fabric rendering of NOT B, placed and routed as a compact one-MUX patch matching M(B,1,0). — NOT B: `B` chooses the opposite constant.

B implies A built with one MUX selected by B, D0 equal to one, and D1 equal to A — `B → A`: when `B=0` the implication is true; when `B=1` it follows `A`.

Actual Cartilage GLSL fabric rendering of B IMPLIES A, placed and routed as a compact one-MUX patch matching M(B,1,A). — `B → A`: when `B=0` the implication is true; when `B=1` it follows `A`.

TRUE Boolean function tied directly to one, with truth vector 1111 and pointer word 1010 — TRUE is a direct constant: `Y=1`.

Actual Cartilage GLSL fabric rendering of TRUE, using one one-constant tile. — TRUE is a direct constant: `Y=1`.

NAND built with two MUXes: the first makes NOT A and the second, selected by B, chooses one or NOT A — NAND: `B=0` forces one; `B=1` passes `NOT A`.

Actual Cartilage GLSL fabric rendering of NAND, placed and routed as a compact shared-A two-MUX patch. — NAND: `B=0` forces one; `B=1` passes `NOT A`.

When B=0, source NOT A uses pointer 11

The high pointer pair is 11.

NOR built with two MUXes: the first makes NOT A and the second, selected by B, chooses NOT A or zero — NOR: `B=0` passes `NOT A`; `B=1` forces zero.

Actual Cartilage GLSL fabric rendering of NOR, placed and routed as a compact shared-A two-MUX patch. — NOR: `B=0` passes `NOT A`; `B=1` forces zero.

XNOR built with two MUXes: the first makes NOT A and the second, selected by B, chooses NOT A or A — XNOR: `B=0` passes `NOT A`; `B=1` passes `A`.

Actual Cartilage GLSL fabric rendering of XNOR, placed and routed as a compact shared-A two-MUX patch. — XNOR: `B=0` passes `NOT A`; `B=1` passes `A`.

A implies B built with one MUX selected by A, D0 equal to one, and D1 equal to B — `A → B`: when `A=0` the implication is true; when `A=1` it follows `B`.

Actual Cartilage GLSL fabric rendering of A IMPLIES B, placed and routed as a compact one-MUX patch matching M(A,1,B). — `A → B`: when `A=0` the implication is true; when `A=1` it follows `B`.

NOT A built with one MUX selected by A, D0 equal to one, and D1 equal to zero — NOT A: `A` chooses the opposite constant.

Actual Cartilage GLSL fabric rendering of NOT A, placed and routed as a compact one-MUX patch matching M(A,1,0). — NOT A: `A` chooses the opposite constant.

Each New Input Adds One Selection Level

A third input selects between two functions from the catalog above. Repeat that decomposition until every branch reaches a constant, and nested MUXes express any Boolean function.

A three-input Boolean function split by a C-selected MUX into F of A B zero and F of A B one — A new input adds one more selection level; the rule does not change.

Actual Cartilage GLSL fabric rendering of a seven-MUX three-input parity tree, showing how one more selector decomposes a three-input function into two two-input branches. — A new input adds one more selection level; the rule does not change.

All 34 Circuits Run In Cartilage

Every one of the 34/34 teaching illustrations has a one-to-one Cartilage route, including five responsive mobile layouts. Shader readback covers 606 passing cases, and each labeled image includes a native-pixel capture.

Cartilage Core commit 48ff6e0 renders the routes through WebGL1 and GLSL. window.cartilage.loadState installs each state, window.cartilage.step advances it, and window.cartilage.readCell reads it back at 96 native pixels per tile.

Every 32×64 state begins with a reconfiguration-port root at (0,0). The checker reads all 2,048 cells before and after each truth-table case and rejects parent-pointer search or any changed parent field. Native zoom and three host-injected boundary cells initialize the capture copy; the GLSL transition and renderer remain identical.

The run executes already routed application circuits. The serial installer supplies the complementary path from configuration stream to placed circuit.

Open the capture, routing, truth-check, and SHA-256 manifest.

The 2020 Logisim Circuits Started The Construction

Five original Logisim circuits precede the paired teaching views and sit outside the 34/34 generated-illustration count.

Original 2020 Logisim configurable MUX network with A, B, ground, power, a four-bit configuration input, and output Y — Original configurable network: the four-bit word controls the two branch meanings, and `B` selects the final branch.

Original 2020 Logisim grid of Boolean functions with S0 equal to zero and S1 equal to zero — Original state: `S0=0, S1=0`.

Original 2020 Logisim grid of Boolean functions with S0 equal to one and S1 equal to zero — Original state: `S0=1, S1=0`.

Original 2020 Logisim grid of Boolean functions with S0 equal to zero and S1 equal to one — Original state: `S0=0, S1=1`.

Original 2020 Logisim grid of Boolean functions with S0 equal to one and S1 equal to one — Original state: `S0=1, S1=1`.

The MUX-algebra construction dates to March 22, 2020; the transistor-level LUT2 follow-up dates to March 23. This edition standardizes variables as A and B and aligns both implication labels with their truth tables.

The Logisim drawings show functional selector networks. A transistor implementation chooses its count through MUX topology, complemented-selector generation, source sharing, loading, and output drive. The original "16 CMOS transistor" LUT2 count corresponds to one such arrangement.

Exact executable definition

function muxAlgebra(a, b, config) {
    const sources = [0, a, 1, Number(!a)];
    const pointer = b ? (config & 0b11) : (config >> 2);
    return sources[pointer];
}

muxAlgebra(1, 1, 0b0001); // AND  -> 1
muxAlgebra(1, 1, 0b0111); // XOR  -> 0

From One Selector To A Reconfigurable Computer

The Logisim-to-LUT learning path grows this rule from LUT1 through LUT6 and connects it to Lattice and AMD/Xilinx FPGA primitives. The physical MUX tiles turn selectors, constants, routes, intersections, and orientation into objects you can arrange by hand. Boolean Algebra Is All That Is Required carries the same construction into storage, configuration transport, ownership, and an extensible fabric.