Boolean Algebra Is All That Is Required

1. The computational claim

“Boolean algebra is all that is required” identifies the computational primitives of the machine:

1. The substrate carries every value as a Boolean value.
2. Boolean functions perform every local combinational transformation.
3. Boolean state holds every configuration, ownership indication, progress indication, and application value.
4. Boolean signals acting through Boolean switching circuitry cause every state change.
5. Another Boolean circuit inside the substrate installs or replaces a circuit; no second-order interpreter stands outside the substrate.

A physical Cartilage realization supplies matter, energy, spatial adjacency, stable Boolean levels, state-holding switching structures, local connections, and finite causal propagation. These physical premises give the Boolean circuit a realizable substrate without adding computational data types or an abstract machine above it.

This paper defines a Boolean process as a retained network of Boolean operations and Boolean storage joined by causal signal paths. Two processes may compute the same extensional truth function while placement, propagation depth, feedback, or ownership gives them different machine behavior. Ordinary truth-table equivalence erases those differences; Cartilage retains them.

A truth table captures a Boolean function after removing the realization's structure and timing. Cartilage instead makes the locally connected Boolean switching process its primitive object. Boolean state selects that process's effective connections and functions.

George Boole's calculus supplies the algebra of Boolean operations and predicates. His writings also discuss successive operations and propositions interpreted over portions of time, while the formal calculus leaves gate delay and next-state scheduling to the realization. This construction combines Boole's value algebra with the causal switching structure that realizes Boolean operations. Explicit physical locality, persistence, and propagation complete the domain without introducing another computational value or transformation algebra.

2. The fixed substrate and the circuits it realizes

2.1 Carrier fabric

Write the carrier lattice as

This regular lattice gives every site four fixed physical neighbors: left, up, right, and down. Its infinite extent expresses potential extension concisely. Every configuration, region, input, transaction, and finite-event causal cone below remains finite or finitely described, so each result requires only finite physical devices and their successively larger finite extensions.

For the computability theorem, one computable rule initializes $L$: it allocates a finite seed and gives every other site the same unclaimed quiescent cell state. The background carries no arbitrary infinite program. Non-Zeno local propagation limits every finite event prefix to a finite claimed causal region. A family of finite physical devices can realize successively larger finite prefixes of this abstract machine. Section 7.4 distinguishes the environment's physical attachment of resources from the abstract CLAIM operation.

Each site contains the same fixed cell circuit. Write $G_0$ for the fixed carrier graph formed only by repeated cells and nearest-neighbor physical links.

2.2 Cell state

Represent the stored Boolean state of site $v$ as

Each field gives the fixed cell a distinct local responsibility:

• $A_v$ records whether the active finite fabric has claimed the site.
• $C_v$ stores the installed role code.
• $P_v$ stores the ownership or parent-direction code.
• $Q_v$ carries an application signal or retains application state.
• $B_v$ holds the fixed loader's working state: configuration shift bits, progress, completion, and edge-history bits.

Implementations may choose the exact number of working bits. The argument requires a finite count and Boolean working transitions. The concrete Cartilage encoding uses a seven-bit installed record: five role bits and two parent-direction bits. A complete robust loader also retains a seven-bit shadow record, a finite bit index, BUSY and FULL indications, the preceding CLOCK value, and the old parent/root relation that carries the active transaction. That retained relation prevents newly received role or parent bits from cutting the route before the transaction finishes.

A fixed local transition circuit governs each cell:

Its arguments comprise the cell's retained bits and the Boolean signals from its four neighbors. This notation names the fixed cell circuit without imposing a global update clock. In an event-driven realization, the causal delay of the participating gates and links precedes each output transition of $F$.

2.3 Installed role alphabet

The five-bit role code directly selects one of 32 effective roles:

• 24 orientations of a 2:1 multiplexer;
• four orientations of a wire;
• one crossing;
• one forced zero;
• one forced one;
• one reconfiguration port.

Four rotations and six ordered choices of two data inputs from the three non-selector sides produce the 24 multiplexer roles. A normal cell broadcasts its selected output toward its neighbors. The crossing carries two opposite routes independently and adds routing convenience without adding a Boolean function.

One value of the same five-bit field selects the reconfiguration port, so the fabric installs a port through the same operation that installs a wire or multiplexer.

2.4 Two graph levels, one computational ontology

The construction separates the fixed carrier graph $G_0$ from two graphs that each cell decodes:

The second decoded graph is

Both decoded graphs omit unclaimed sites. In $T(A,C,P)$, the reconfiguration-port role makes a claimed cell a component root, and its two direction bits select external ingress orientation instead of an internal parent edge. Every claimed non-port cell contributes the local parent edge that its two direction bits select. Root status cannot follow from $P$ alone; role and direction together determine both root status and the effective port behavior in $G$.

Fabrication fixes the carrier graph. Fixed Boolean cell circuits decode the effective circuit and ownership graphs locally from Boolean state, without an external interpreter. When a configuration stream changes $C$ or $P$, the same fixed substrate changes the effective graphs it presents.

An SRAM FPGA uses the same logical recursion. A fabricated FPGA already contains a Boolean sequential circuit with configuration storage, routing selectors, lookup structures, registers, and loading circuitry. Let $U$ denote that fixed circuit and $C$ its configuration state:

The bit pattern $C$ specializes the fixed circuit into $f_C$. Cartilage localizes that specialization and makes it recursively available through owned ports.

3. Boolean completeness, storage, and causal time

3.1 Multiplexer completeness

One 2:1 multiplexer computes

Constants zero and one immediately give

and Shannon expansion recursively constructs every finite Boolean function:

The earlier MUX Algebra paper develops the complete two-variable case through nested selection notation, a four-bit configuration, and all 16 Boolean functions of two inputs.

Multiplexers, constants, and stored Boolean values therefore implement the cell's fixed loader, counters, decoders, progress flags, ownership tests, routing selectors, and application logic. The fabric interprets, moves, and installs configuration bits with the same logical primitives as the circuits those bits install.

3.2 Storage

A configured MUX and a positive-delay feedback route create a retained bit. Connect the first data input to the MUX's prior output through that route, connect the second data input to new value $d$, and use enable $e$ as selector. The following relation governs its Boolean next value:

When $e=0$, the MUX selects and retains delayed prior value $q$. When $e=1$, it selects $d$, which then returns through the feedback path. Holding $e$ and $d$ through the declared setup, propagation, and hold intervals yields an addressable one-bit latch. A physical latch, flip-flop, charge-holding node, or other bistable switching structure realizes the relation causally. Boolean circuits provide the load, hold, and feedback paths; Boolean state holds the value; the finite initial configuration supplies its initial value.

Purely equational Boolean algebra leaves transition duration unspecified. Cartilage adds a causal, non-Zeno realization that allows only finitely many causally successive local transitions within any finite physical interval. Once the construction retains finite propagation, feedback creates memory and transitions order events without requiring a universal time coordinate.

3.3 No operational global state

Each cell responds only to its retained bits and signals from adjacent cells. Events without a causal path need no ordering. A mathematical observer may describe values on a chosen cut through the event history, while the machine itself reads, constructs, and updates only local causal state.

The browser emulator evaluates the lattice through repeated framebuffer passes. Each pass advances simulated propagation by one increment as part of the emulator's integration schedule; the modeled Cartilage machine receives no distributed clock from those passes.

4. Finite regions, ownership, and ports

4.1 Valid owned region

Represent one current component of the decoded ownership forest as the finite owned region

Its components satisfy these exact conditions:

• $V_R\subset L$ contains a finite connected set of claimed cells;
• $p_R\in V_R$ names the only cell in $V_R$ with the installed reconfiguration-port role;
• every other cell in $V_R$ has a non-port role and one parent direction that points to an adjacent cell in $V_R$;
• following parent directions from any cell reaches $p_R$ after finitely many steps;
• parent directions form no cycle inside $R$;
• transaction closure keeps every child that a member accepts inside $V_R$; no cell outside $V_R$ joins the retained transaction tree.

Thus $T_R$ forms a rooted spanning tree for exactly one ownership component. A nested child port roots a different component, so ordinary traversal of $V_R$ stops at that transaction-closed boundary unless the owner separately selects the child through its port. The child owns its port as root. The parent/ingress code selects one local application side for DATA, and the next application side in the fixed rotational convention supplies CLOCK. One logical owner drives these two distinct ordinary Boolean paths. Separate configuration-overlay channels connect the port to the child's ownership tree, and the single-driver condition prevents configuration-ingress contention.

A convenient numeric convention maps $0=\text{left}$, $1=\text{up}$, $2=\text{right}$, and $3=\text{down}$. The port root uses those same two bits for its external DATA ingress orientation; the conventionally adjacent side carries CLOCK, and the port role itself supplies root status.

Define ownership-tree depth as

The finite size of $R$ guarantees a finite $D(R)$.

4.2 Ownership is authority, not address space

Under the valid-tree and exclusive-driver contract, the parent field provides two related capabilities:

1. it routes configuration control locally to a cell; and
2. it identifies the unique enclosing port authorized to replace that cell through a well-formed transaction.

A physical signal path to the child's port gives the owner all addressing needed for a transaction. The port and its downstream tree define the operation's scope without a global coordinate.

The ownership tree carries configuration authority. Ordinary configured storage and routes can separately implement an application heap as an encoded graph of objects and references, including sharing and cycles, while the physical ownership relation remains a tree.

4.3 Owner and loader responsibilities

The owning application region produces:

• an installation sequence of seven-bit cell records;
• a Boolean DATA waveform that carries those records;
• a Boolean CLOCK waveform that delimits record bits;
• a safe interval between CLOCK transitions for its particular child region.

Before replacement, the owner poisons, fences, or otherwise isolates the child's application boundary. It blocks ordinary application traffic until release, allowing the base theorem to guarantee a correct final replacement while the intermediate commit wave remains behind the fence.

Fixed loader circuitry throughout the child determines:

• the incomplete cell that receives the current bit;
• the one-neighbor-at-a-time route for CLOCK and DATA;
• completion of each cell record;
• completion of each subtree;
• completion of the whole region.

A processor, finite controller, dataflow network, or dedicated bitstream generator can serve as owner, and each takes form as a configured region of the same fabric. Fixed Boolean circuitry in every cell performs loading directly, without hidden processor software.

5. The finite reconfiguration transaction

5.1 Installed record

The base role alphabet gives each cell this installed record:

Five bits select one of 32 roles, and two bits select one of four parent directions. Implementations may add optional application-state initialization or inherited-record fields while the seven-bit base record already supplies Boolean closure and universal computation.

Boolean state also recognizes CLOCK edges. Let $c$ represent the current CLOCK input and $c^{-}$ retain its preceding value:

Finite Boolean functions of these edge indications and the loader's retained bits determine the bit index, FULL transition, commit enable, and reset/release conditions.

5.2 Deterministic traversal

Each cell orders possible child directions relative to its parent direction. Any fixed order works; this construction uses right-relative, forward-relative, then left-relative.

Every loader applies the same local rule:

1. When an ordered incomplete child exists, forward CLOCK and DATA to the first one.
2. After every child completes, consume incoming DATA bits in the local staging register.
3. After the local record fills, mark the cell complete toward its parent.

In COMMIT state, a complete node forwards commit-high to every retained transaction child. Each leaf then copies its shadow record; each internal node waits for every retained transaction child to acknowledge before copying. Commit-low and release follow the same retained route. Newly active roles and parent values never control the transaction that installs them.

This rule generates a depth-first postorder traversal without a traversal stack. Ownership pointers embed the stack in space, and completion bits mark subtrees that no longer require data.

When a cell observes its first transaction event, its loader retains the current parent direction and transaction-root status. Those bits define the transaction route for loading, completion, commit dissemination, and release while incoming records wait in shadow latches.

After all cells complete loading, one additional commit cycle travels through the complete transaction tree. Leaves copy shadow role and parent records into active latches first; each internal node copies after its children acknowledge. Every cell continues routing commit and its guarded return phase along the retained route, then a postorder release clears transaction working state.

For the base theorem, a valid final ownership forest partitions every cell of $R$ into disjoint rooted components. Each installed port roots exactly one component, and every non-root holds a non-port role whose parent direction points to an adjacent cell in the same component. Repeated parent following ends at that component's port. The original root $p_R$ remains a port and preserves the enclosing owner's interface.

An immediately usable nested hierarchy adds one local wiring condition. For every new port root, the DATA and CLOCK driver sites that its ingress orientation selects must exist, occupy one different component that acts as immediate owner, and drive that port. An edge from each owner component to its child must form an acyclic component graph rooted, within $R$, at the component containing $p_R$. This condition turns every additional component into a genuine locally driven child. A valid partition may also reserve extra ports without driver wiring for later use. A separate allocation operation handles deletion or return of capacity to an enclosing region.

The finite overlay epoch lets a transaction install new ports and parent directions while keeping those new values from redirecting their own installation. Boolean latches, completion bits, and multiplexers in the fixed loader implement the entire mechanism.

5.3 Transaction modes and termination

A finite Boolean mode field gives every loader these protocol states:

• IDLE: retains no transaction route and keeps FULL clear.
• LOAD: retains the transaction route while the first incomplete frontier consumes DATA on rising strobes.
• FULL: marks the local shadow record and every transaction-child subtree complete and asserts FULL toward the transaction parent.
• COMMIT: forwards a commit-high event through every FULL transaction child.
• COMMITTED: records the shadow-to-active copy and returns commit acknowledgement toward the root.
• RELEASE: clears FULL, shadow-valid, acknowledgement, and transaction-route state in a safe postorder during commit-low/release.

The first loading strobe entering an IDLE region establishes BUSY/LOAD and makes every visited cell retain its current transaction route. Seven rising strobes at a selected cell fill its shadow record; the next guarded low phase sets that cell FULL. FULL then stays monotone until release.

After the root sees every transaction child FULL and sets its own FULL indication, the next rising strobe means COMMIT rather than an eighth data strobe. Each COMMIT node first asserts commit-high on every retained transaction-child output. A leaf copies shadow to active state and acknowledges its transaction parent. An internal node waits for all transaction-child acknowledgements before copying and acknowledging. The root names its acknowledgement COMPLETE.

The owner fences the application boundary, holds the commit phase through its declared causal guard, and lowers the strobe. RELEASE then traverses the retained tree. Each releasing node asserts RELEASE_ACK on its retained parent edge and holds that ACK and route through a characterized one-hop capture guard, giving the parent time to latch it. An internal node starts its capture guard only after it latches every child RELEASE_ACK, then clears transaction state after the guard. This order makes the root clear last. The bound ${\Lambda }_L(R)$ includes the complete release path and its capture guards. COMPLETE returns low, the retained overlay disappears, and later transactions decode ownership only from the newly installed forest.

Finite Boolean state and Boolean functions implement every mode, child test, monotone flag, fan-out enable, acknowledgement, copy, and clearing condition.

5.4 Traversal lemma

Lemma 1 — unique finite coverage. In every valid finite owned region $R$, the local traversal rule visits each cell exactly once and finishes at the root.

Proof. In a one-cell tree, the childless root consumes one record and completes. Assume unique finite coverage for every tree smaller than $n$. For a tree of $n$ cells, the root forwards the stream to its first incomplete child. That child subtree contains fewer than $n$ cells, so induction makes it consume one record per cell and complete. The root then selects the next incomplete child in its fixed order and never selects a completed child again. After every child subtree completes, the root consumes one record and completes. The ownership tree assigns every non-root node to exactly one child subtree. Shadow records and newly committed records leave the retained transaction route unchanged, so role and parent replacement preserve the induction. The traversal therefore omits and repeats no node. ∎

The owner orders records by transaction-tree postorder. Within each record, it sends five role bits—two orientation bits and three mode bits—followed by two parent bits in the declared least-significant-bit-first order. For $N=|V_R|$, loading consumes exactly $7N$ rising strobes. One additional guarded cycle distributes commit; completion and release add no cell record.

5.5 Installation lemma

Lemma 2 — local Boolean staging and installation. Seven DATA bits separated by valid CLOCK transitions, followed by commit, make the selected cell's installed record equal those seven bits through Boolean state transitions alone.

Proof. On each designated CLOCK event, the fixed loader shifts one Boolean DATA value into a seven-bit shadow register. A finite Boolean counter or equivalent shift-completion signal recognizes the seventh received bit and marks loading complete for that cell. The later commit event enables a copy from shadow into the active role and parent latches. Finite Boolean functions with retained Boolean state perform shifting, counting, equality detection, completion, enabling, and copying. ∎

5.6 Commit-and-release lemma

Lemma 3 — finite commit and safe release. For every finite transaction tree with all cells FULL, one commit-high event makes every cell copy its shadow record exactly once and makes the root assert COMPLETE. The following release event clears each retained transaction route exactly once while preserving every commit, acknowledgement, and release path until its final use.

Proof. A FULL leaf has no transaction child, so it copies once, latches COMMITTED, and acknowledges. Assume the result for child subtrees shorter than height $d$. A node at height $d$ forwards commit to all children; induction makes every child subtree commit and acknowledge within finite causal depth. The node then copies once and acknowledges, allowing the root eventually to receive all acknowledgements and assert COMPLETE. During release, a leaf asserts RELEASE_ACK and holds its route through the one-hop capture guard, so the parent latches the acknowledgement before the leaf clears. Inductively, each internal node latches every child acknowledgement, asserts its own, and retains its route through the same guaranteed capture before clearing. The root clears last. Retained transaction paths carry the entire proof; active and shadow parent values never participate. ∎

5.7 Endogenous-reconfiguration theorem

Theorem 1 — Boolean closure under finite reconfiguration. Take a valid finite owned region $R$ with one designated configuration driver and a quiescent application boundary. Let its owner emit a finite valid configuration transaction at $p_R$, with new role and parent records that jointly decode to a valid final ownership forest. The transaction then installs the specified Boolean record in every cell of $R$, leaves every installed record outside $R$ unchanged, terminates, releases a well-defined final circuit, and uses only computational mechanisms within the Boolean fabric.

Proof. Lemma 1 makes the fixed local traversal deliver one record to every cell and terminate. Transaction closure and child-only forwarding keep the stream inside $R$. Lemma 2 makes Boolean sequential circuitry stage each record, and Lemma 3 commits and releases the finite tree while preserving every path until its final use. Commit advances causally rather than simultaneously; the application fence keeps the intermediate circuit outside application use. After root acknowledgement and release, the stipulated records jointly decode the valid final forest. An installed Boolean role implements the port. Boolean transaction-route and completion bits determine routing. Boolean signals transport configuration. Boolean state holds the application and ownership fields. Section 7.3 constructs the owner that emits finite Boolean DATA and CLOCK waveforms as another finite Cartilage configuration. Production, transport, traversal, progress recognition, commit, release, and the resulting circuit therefore all operate as processes of the same fixed Boolean substrate. ∎

When the final configuration satisfies Section 5.2's driver-wiring and component-acyclicity condition, a newly installed port can receive another locally produced configuration transaction and instantiate its own finite child region. Each recursive level uses the same machine.

6. Timing without a clock system

6.1 CLOCK is a local transaction strobe

CLOCK serves as one Boolean transaction signal from an immediate owner into one child port. It may run aperiodically and remains local to that transaction rather than forming a clock domain or global timebase. During loading, the fixed overlay sends CLOCK and DATA only toward the first incomplete node that the transaction tree selects. During commit and release, the strobe traverses the retained finite tree with no requirement for simultaneous arrival at all cells.

6.2 Causal size and bounded-delay model

Define the region's maximum causal path as

This path runs from the owner-side neighbor through the port ingress to a region cell. The added one counts the physical owner-to-port forwarding stage, including a one-cell region. Causal radius, rather than bounding-box width alone, supplies the relevant linear size. A serpentine tree in an $L$-by-$L$ area may reach $\hat{h}(R)=\Theta (L^2)$. When allocation maintains a shortest-path, breadth-first, or monotone tree in a $W$-by-$H$ region,

For every other tree shape, the owner uses the actual depth.

Use ${\Lambda }_H(R)$ as a static upper bound on every complete causal dependency that must close during a high phase. It covers an ordinary loading rise reaching the selected receiver and, during commit, fan-out, local copies, and acknowledgement back to the root. It also covers the shortening of a high pulse at any participating receiver from unequal rise and fall paths.

Use ${\Lambda }_L(R)$ as the corresponding low-phase bound. It covers falling-edge propagation, FULL changes, completion returning far enough to select the next frontier, new DATA reaching that frontier, final postorder release, and low-pulse shortening from unequal fall and rise paths.

These whole-path bounds come from the fixed cell netlist and finite retained transaction tree, rather than from single-hop delay. Each protocol phase traverses a fixed finite number of tree paths, so fixed implementation constants $a_H,a_L,b_H,b_L$ and a worst-case tree-level delay $\Delta$ satisfy

Gate-level static timing analysis of the concrete loader establishes these constants; geometric dimensions alone cannot supply them.

Use $t_{su}$, $t_h$, $t_{pw,H}$, and $t_{pw,L}$ for receiver setup time, hold time, high pulse width, and low pulse width. Let $m>0$ provide engineering margin. Cell and transition delays may differ while remaining within the declared whole-path bounds. Open-loop bounded-delay correctness therefore requires bounded propagation and metastability resolution.

6.3 Owner phase contract

Define the conservative high-phase guard as

and the low-phase guard as

The owner chooses actual finite source phase lengths $H_R$ and $L_R$ that satisfy

For each bit, the owner executes this protocol:

1. Present the next DATA value while CLOCK remains low.
2. Hold DATA and CLOCK low for at least $L_R$.
3. Raise CLOCK while holding DATA unchanged.
4. Hold CLOCK high for at least $H_R$.
5. Lower CLOCK and advance DATA only when step 1 begins the next low phase.

The high bound gives the final high-phase consequence, receiver hold time, and pulse-width requirement time to finish before the source lowers CLOCK or changes DATA. The low bound gives completion, rerouting, any applicable release, and newly presented DATA time to settle with setup margin before the next rise. These whole-path bounds remove any need to assume equal delays or guess a forward/return coefficient.

Every finite region has finite $\hat{h}(R)$, $H_R$, and $L_R$, while unbounded causal radius prevents one positive fixed configuration rate from covering every extension. A periodic description may write

The owner may also use an aperiodic sequence.

6.4 Timing theorem and finite completion bound

Theorem 2 — finite-region timing closure. Assume a finite valid transaction tree, empty initial loader-progress bits, one owner, a quiescent application boundary, retained transaction routing, and the bounded-delay owner phase contract. The first $7N$ rising strobes, where $N=|V_R|$, then reach exactly one cell each in deterministic postorder and deliver seven consecutive bits per cell. One additional guarded cycle commits the shadow records. The transaction finishes and releases within finite time while using no global clock, synchronized local clocks, global or local H-tree, continuously running clock-distribution network, crystal oscillator, GPS, or external time reference. The retained tree deliberately routes the finite transaction strobe and tolerates bounded skew.

Proof. Lemma 1 supplies a unique finite postorder at the abstract protocol level. By definition, the high and low inequalities dominate every whole causal dependency through which one source transition can affect interpretation of the next. Induction over the finite source-transition sequence therefore gives the physical bounded-delay execution the same observations as the serialized traversal. After $7N$ rising strobes, every shadow record holds all seven bits. Lemma 3 and the guarded final high and low phases commit, acknowledge, and release the retained tree even when new roles or parent bits differ. Every step uses causal switching within this one finite transaction rather than simultaneous switching or a shared external phase. ∎

When the owner chooses constant finite phase lengths $H_R$ and $L_R$ together with an actual finite initial settling interval $L_{\mathrm{i}\mathrm{n}\mathrm{i}\mathrm{t}}$, this equation gives source-sequence duration through release:

The initial guard satisfies

Here ${\Lambda }_{\mathrm{i}\mathrm{n}\mathrm{i}\mathrm{t}}(R)$ bounds the path from initial DATA presentation to stability at the first selected receiver. The equality describes the source sequence for the chosen guards, while an owner may wait longer. Substituting characterized finite maximum delays for the owner or its delay replicas produces a physical worst-case completion bound. Either treatment supplies every finite region with a finite witness schedule.

6.5 Producing the guard inside the owner

Two matched delay replicas made from the same Boolean and wire cells let the owner produce the required guards without a crystal. If one replica stage has characterized minimum delay ${\delta }_{\mathrm{r}\mathrm{e}\mathrm{p},\mathrm{m}\mathrm{i}\mathrm{n}}$, choose finite lengths $n_H,n_L$ such that

A Boolean phase controller raises CLOCK, launches a token through the high-phase replica, and lowers CLOCK when the delayed token returns. It then advances DATA, launches a token through the low-phase replica, and raises CLOCK when that token returns. This bundled-delay sequencer replaces a free-running time reference or balanced clock H-tree. Its design compares minimum replica delay against maximum protected-path delay with process, voltage, temperature, loading, and skew margin. Internal commit and release acknowledgements remain part of the finite loader protocol. Root COMPLETE can support fault detection or adaptive speed, while replica delay determines nominal phase length.

For a larger finite child, the owner instantiates a longer finite delay replica or emits wider finite phases by another method. Ordinary Boolean input or retained initialization supplies the owner's initial event.

The browser implementation directly emulates this guarded discipline. One framebuffer update advances local propagation by one neighboring step, and the owner changes the modeled configuration strobe only after a fixed number of updates. Those passes emulate closure time without acting as an architectural global clock.

7. Programming and ordinary machines

7.1 Programming is installation

A program for the fabric gives an owner a finite description to convert into configuration records and local application data. The description may enter as initial input in the same way that another model receives a bitstream, machine-code image, or Turing-machine tape. After the fabric installs a suitable generator or processor, that region can compute further configuration streams internally.

Program, configuration, and application data share one ontology. Their routes through the fabric and the Boolean latches they control distinguish their roles.

7.2 Finite Boolean circuits

Theorem 3 — finite-circuit embedding. Every finite Boolean circuit admits a finite Cartilage configuration with identical Boolean input-output behavior after propagation settles.

Proof. Shannon expansion replaces every gate with a finite multiplexer-and-constant network. Embed the resulting finite directed netlist in a finite rectangle of the grid. Wire roles carry routed segments, crossing roles carry two independent crossing routes, and multiplexer roles perform logic. Presenting one cell output to multiple routed successors supplies fan-out. The finite source netlist yields a finite replacement and planar routed embedding, which computes the same Boolean function after its finite propagation depth settles. ∎

7.3 Sequential circuits and stored-program processors

Theorem 4 — finite transition-system embedding. Take any finite deterministic Boolean transition system

A compatible finite-delay discipline gives this system a finite Cartilage configuration whose state after each declared local publish event equals $q_n$.

Proof. Theorem 3 embeds finite combinational function $F$. Add two finite banks of Section 3.2 retained elements and one retained phase bit. At every moment, one active bank supplies the sole state input to $F$ while the other remains inactive. During evaluation, hold $x_n$ and the active bank fixed, let $F(q_n,x_n)$ settle, and load only the inactive bank. After setup and hold finish, close that bank. During a nonoverlapping publish phase, change the phase bit so the completed inactive bank becomes active. Hold the former active bank unchanged until the selector transition and all external outputs settle, then reuse it as the inactive bank for the next transition.

The combinational network never reads the bank under write, which prevents transparent-latch race-through. The evaluate guard exceeds the maximum path from active state and input through $F$ into the inactive bank; the publish guard exceeds the maximum phase-selector and output path. These finite static timing bounds match the finite configuration. A fence delays observations until after the publish guard, so physical bit and selector skew need not imply mathematical simultaneity. Induction on publish events gives the selected bank exactly $q_n$ and the next bank exactly $F(q_n,x_n)$. A fixed finite phase controller built directly from the MUX latches of Section 3.2 generates evaluate, close, publish, and return; acknowledgements or bundled-delay guards keep it from advancing early. This finite Boolean controller serves only its local region and invokes no global clock or theorem-level oracle. ∎

Finite Boolean transition systems realize registers, finite memories, arithmetic units, instruction decoders, program counters, buses, and control units. Therefore every finite memory capacity $n$ gives a conventional von Neumann computer $V_n$ a finite Cartilage configuration.

The construction works uniformly. Given a finite Boolean or RTL description and finite memory bound, mechanical Boolean decomposition and a finite placement-and-routing search enumerate successively larger rectangles until they find an embedding. Engineering determines efficiency; computable search establishes existence without prior knowledge of the final layout.

Corollary — in-fabric owner. A finite controller can read a finite configuration description and emit Section 6's DATA waveform and guarded CLOCK phases. Its finite Boolean transition-system realization gives it, by Theorem 4, a finite Cartilage configuration. The same fabric therefore realizes Theorem 1's Boolean source internally.

Corollary — finite recursive composition. For every finite nesting depth $d$, a Cartilage region can configure a child hierarchy of depth $d$ entirely within the fabric.

Proof. Depth zero requires no child transaction. Assume internal configurability through depth $d$. Theorem 1 lets the owner install another port, its local DATA/CLOCK driver wiring, and the finite owner controller from the preceding corollary while satisfying Section 5.2 component acyclicity. That child configures a depth-$d$ hierarchy and thereby produces depth $d+1$. ∎

A conventional compiler can produce the instruction bits stored in $V_n$. The compiler creates Boolean input and can itself take form as another finite or extensible Boolean machine, so compilation introduces no new computational primitive.

A Turing machine provides a convenient proof organization, and a von Neumann processor provides a convenient programmable organization. Both inhabit the Boolean fabric as structures of Boolean state and switching.

7.4 Potentially unbounded storage

For the abstract universality theorem, every site outside the finite seed starts in the same computable unclaimed state $A_v=0$. An unclaimed cell responds only through a fixed local CLAIM interface and otherwise ignores application and configuration traffic.

A finite boundary controller annexes one adjacent site through this Boolean protocol:

1. A claimed boundary cell asserts CLAIM toward one adjacent unclaimed site.
2. If several neighbors request simultaneously, the unclaimed cell applies one fixed direction priority; a well-formed allocator normally prevents that contention.
3. The selected cell sets $A_v=1$, points its parent direction toward the requester, keeps a quiescent installed role, and asserts ACK on that edge.
4. After ACK, the requester treats the cell as an owned leaf and may include it in a finite configuration transaction.

Fixed finite Boolean circuitry implements CLAIM, priority, the allocated latch, parent installation, and ACK. Local edges identify cells, and the repeated protocol grows the active size without a global coordinate or oracle.

Potential extension supplies universality: every finite claimed region borders quiescent sites in the computably blank carrier, and the finite CLAIM protocol can repeat without a predetermined bound. Each active machine at each finite event prefix still uses finite memory.

A locally linked path of finite symbol cells realizes an unbounded tape through potential extension. When the simulated head reaches the current end, the allocation controller claims one adjacent quiescent cell and installs its blank-symbol role. Every finite event prefix claims only finitely many cells and touches only a finite causal region.

The fabric can also generate a uniform sequence of finite von Neumann configurations $V_1,V_2,\dots$, while a running machine organizes newly claimed blocks as linked or segmented storage. Here “heap” means an application-level graph of dynamically allocated storage, distinct from both a sorted binary heap and the ownership tree.

A finite physical device receives each additional physical cell or module through an explicit environmental resource action. Once that resource exposes the standard local interface, Boolean circuitry performs CLAIM and all later allocation and configuration. This premise separates the mechanical supply of matter from the computation of the existing finite circuit.

7.5 Computability theorem

A function computation starts with finite input and the computable quiescent background. A declared transition on the designated Boolean HALT output terminates it, and finite Boolean values at designated output ports provide the result. The program treats exact analog transition times as physical behavior rather than output data.

An admissible configuration uses one of two constructive execution semantics. In the delay-robust form, all legal delay assignments that satisfy the timing contract agree on termination and result: for each input, every legal execution either diverges or eventually asserts HALT with the same finite output. In the scheduled form, one explicitly specified computable fair scheduler resolves every machine-visible race or arbitration, and computable specifications provide all timing bounds needed to generate the execution. That scheduled execution defines the computed partial function. In both forms, the finite machine description supplies at least one computable fair legal event schedule. The delay-robust form uses that schedule only as a simulation witness; its result remains invariant across all legal executions. The program gains no oracle from metastable amplitudes, noncomputable real delays, relative-delay races, or exact-time measurements.

Theorem 5 — Turing equivalence under constructive premises. With finitely described initial conditions, computable local cell circuitry, non-Zeno finite causal propagation, constructive execution semantics, and potentially unbounded finite extension, Cartilage computes exactly the partial recursive functions.

Proof, lower bound. Theorem 4 implements finite sequential control. A locally linked path implements tape symbols and head position, while potential extension adds another blank symbol cell whenever the computation requires one. Cartilage therefore simulates any ordinary Turing machine.

Proof, upper bound. Each cell has a finite state alphabet and a computable local transition. Starting from a finite or computably generated initial description, a Turing machine can enumerate the finite causal events that affect any finite event prefix under the specified computable fair scheduler. Locality, quiescence beyond the reached cone, and non-Zeno propagation keep each prefix finite. For scheduled semantics, the simulator follows the declared scheduler directly. For delay-robust semantics, it chooses any fixed computable fair legal scheduler that satisfies the bounds; admissibility makes its halting behavior and output equal every other legal execution. Computable local CLAIM and configuration protocols add only finitely described active cells. HALT and output supply finite Boolean observations instead of arbitrary real-time measurements. The simulator therefore halts exactly on the Cartilage computation's domain and returns the same finite output, making every Cartilage-computable partial function partial recursive. ∎

The theorem's computable initial-condition premise gives the infinite background one uniform quiescent rule. Supplying an arbitrary noncomputable infinite pattern and making it queryable would add an oracle through the initial condition rather than generate power within the Boolean substrate. Ordinary quantum computation likewise changes complexity bounds while preserving this computability classification.

8. Classical machines as organizations of one substrate

Organization and resource discipline create the familiar distinctions between machines while every one of them uses the same logical primitives:

• A fixed finite active region realizes a finite-state sequential machine.
• A finite controller and one unbounded last-in-first-out path realize a pushdown discipline.
• A finite controller, extensible symbol path, and movable head realize a Turing tape.
• Finite memory turns a processor configuration into a finite von Neumann machine.
• Uniformly extensible linked storage blocks provide potentially unbounded general storage.

A pushdown automaton's restricted access discipline makes it weaker than a Turing machine even though both use Boolean logic. Universality requires more than unbounded passive storage: each newly available Cartilage cell contributes configurable logic, routing, and retained state, and the explicit tape construction organizes those resources into a universal machine.

9. The seven-bit direct-encoding optimum

The selected role and ownership alphabet admits an exact information-theoretic result.

With 32 directly selectable roles, every fixed-length direct role code needs at least

bits. Four parent directions require at least

bits. Independent selection of role and parent creates $32·4=128$ installed records and therefore requires at least seven bits. The base Cartilage record attains this bound.

Seven bits therefore achieve the optimum for this selected 32-role direct alphabet and four-direction ownership encoding. Global minimization of a universal cellular substrate, complete-loader latch count, dimensionality, and the need for a direct crossing role constitute separate optimization problems with different objective functions.

10. Finite realization and the emulator

Every physical Cartilage device occupies a finite extent. Tiling devices or extending an exposed boundary produces successively larger finite machines. The theoretical potential-extension premise removes a fixed maximum across that family in the same way that an abstract Turing tape removes a fixed tape bound.

The browser/GPGPU implementation packs every logical cell into finite Boolean state and repeatedly applies the fixed local transition. Full-texture passes advance the simulation and emulate nonzero propagation time while remaining invisible to configured Cartilage application logic. Ordinary modeled CLOCK and DATA signals enter through a local port and move through the ownership tree.

The browser executes the finite cell transition, role decoding, local ownership representation, serial loading, progress flags, guarded local strobe, nested ports, and a parent-preserving configuration transaction. Completing the general substrate contract adds a retained transaction-route epoch, acknowledged commit/release, arbitrary safe reparenting, and the quiescent-site CLAIM interface for uniform lazy allocation. A shader, ASIC, FPGA realization, or modular assembly reaches the full theorem when it implements those observable local mechanisms and meets the declared physical timing bounds.

The public Cartilage Core repository supplies a second executable layer. Its SystemVerilog fabric implements a continuous combinational application plane, locally routed configuration clocks, real local positive and negative configuration edges, and a three-bit route shadow that preserves the active path through handoff. Its self-checking Verilator testbench installs all 36 seven-bit records of one 6x6 image and checks all four rows of an interior-MUX AND circuit. Together, the browser and RTL establish two logical implementations of the local mechanism. The retained-route epoch, acknowledged commit/release, arbitrary safe reparenting, lazy CLAIM, gate-level timing closure, and silicon realization form the next integrated engineering path.

11. Constructive premises and exact domain

Eight premises define the machine and make every theorem constructive:

P1 — Boolean cell circuitry. Finite Boolean circuits with retained Boolean state perform every cell's application and loader transformations.

P2 — Local carrier. A fixed finite number of local physical links connects each cell to its neighbors.

P3 — Causal realization. Signal and storage transitions exhibit characterized positive, finite behavior. This behavior includes Section 6's worst-case loader bounds and a non-Zeno guarantee that permits only finitely many causally successive local transitions in finite time.

P4 — Valid ownership. Every reconfigured region occupies one finite transaction-closed component of $T(A,C,P)$. Its retained claim, role, and direction fields decode a rooted acyclic tree with exactly one port root. The protocol suspends integrity-repair mutations during the transaction and keeps every cell claimed throughout the base transaction. Before release, newly installed role and direction fields combine with those claim bits to decode a valid final forest. Every claimed nested hierarchy also meets Section 5.2's explicit driver-wiring and component-acyclicity condition.

P5 — Owner timing. The owner calculates a separation bound from the target region's finite causal depth and applies it between configuration transitions.

P6 — Constructive initialization, execution, and observation. Finite or computable procedures generate initial configurations, input streams, CLAIM actions, timing signals, HALT, and output observations. The machine description supplies a computable fair legal event schedule. Either termination and output remain invariant across all legal delays, or a specified computable fair scheduler with computably specified timing bounds resolves machine-visible nondeterminism. The program observes Boolean results rather than using exact analog time, arbitrary real delays, race outcomes, or metastable quantities as oracle values.

P7 — Potential extension. A computably uniform quiescent background surrounds the theoretical carrier, and the finite Boolean CLAIM protocol may annex adjacent sites without a predetermined bound. The environment supplies physical attachment as a resource premise for each finite implementation.

P8 — Exclusive transaction. One designated owner drives each child's configuration ingress, and transaction exclusion prevents another transaction from mutating that child before release.

Together these premises establish the theorem's exact constructive domain:

• The physical realization supplies spacetime and energy; Boolean equations govern computation within that realization.
• The timing contract governs configured asynchronous behavior, while arbitrary asynchronous circuits require their own hazard analysis.
• The application fence exposes newly installed logic after completion and release.
• Local causal observations replace a machine-wide physical snapshot.
• Configurable active extension, rather than unbounded passive memory alone, supplies universality.
• The computably uniform background supplies no noncomputable infinite pattern; any queryable pattern of that kind would enter through the initial condition as an external oracle.
• Under the constructive premises, Cartilage computes exactly the Turing-computable partial functions.
• The seven-bit optimum applies to the selected direct role alphabet and four-direction ownership encoding.
• Parent pointers express configuration authority; cryptographic protection against a physically adversarial driver requires additional security mechanisms.
• The browser shader establishes modeled local behavior; electrical characterization establishes the limits of a future physical implementation.

12. Conclusion

Cartilage starts from one fixed Boolean cell circuit and repeats it across a local fabric. Boolean configuration bits select each effective application role. Boolean parent bits establish local ownership. Boolean loader state routes Boolean DATA and CLOCK through a finite region. Boolean completion state governs record and subtree progress. Each installed result forms another Boolean circuit capable of generating and installing further Boolean configurations.

The same substrate therefore serves as both the configured machine and the machine that performs configuration. Programming changes organization without changing computational ontology.

Causal propagation of switching events gives time its operational role. A finite owner waits for the causal depth of its finite region, and a finite path in the same fabric can produce that interval. The selected transaction tree routes a finite local strobe with bounded, tolerated skew. This mechanism replaces global synchronization, global or local H-trees, continuously running clock-distribution networks, crystals, GPS, and non-Boolean timing controllers.

Finite Boolean circuits, sequential machines, conventional processors, tapes, stacks, and linked memories all emerge as configurations and resource disciplines within this substrate. Potential extension removes a fixed resource bound while retaining the same logical primitive, yielding exact Turing equivalence under constructive initial conditions.

Across application behavior, configuration transport, ownership, traversal, commit, release, and circuit replacement, every machine-visible value and computational transformation remains Boolean. The explicit carrier, causal-propagation, non-Zeno, timing, and resource premises turn that statement into a constructive machine—and open a direct path from browser execution and RTL to a recursively reconfigurable physical computing fabric.