One FPGA pin synthesizes 106 independently moving RF channels across 3 MHz. One-bit arithmetic produces 3.375 million 64-bit products or 6.75 million binary32 quotients per second on an HX8K. Cartilage installs and replaces spatial circuit regions. Raw WebGL turns a browser texture into a visible computing machine.
Greenforest I/O develops the mechanism itself—circuit, shader, fabric, RTL, board, or physical process—so an engineer can run it, understand it, and carry it into a product or research program.
Why Wi-Fi Needs a Real-Time Radio
Build the path from I/Q samples to an encrypted HTTP page: Barker correlation, bit-serial multiplication, the 10 µs ACK deadline, association, WPA2 keys, CCMP, DHCP, ARP and TCP. Includes byte layouts, arithmetic, state transitions, full source and build scripts.
Read the implementation guide and download the C++ and RTL
Four Machines, Three Scales
Two clock-by-clock arithmetic schedules, a GPU-wide state machine, and a recursively reconfigurable fabric expose the structure that conventional stacks hide.
Correctly rounded binary32
Raw IEEE binary32 operands enter LSB first. Three serial multipliers, eight add/subtract engines, and three comparators carry significand, exponent, and sign through one-bit internal streams and accept another finite-normal division every 32 clocks at 216 MHz.
Download the open RTL, rebuild files, utilization, and physical run
Continuous arithmetic
The 254-LUT4, 635-flip-flop SystemVerilog core accepts the next operand word every 64 clocks at 216 MHz. Twelve copies fit the HX8K and deliver 40.5 million low 64-bit products per second.
Download the RTL, build, utilization report, and physical results
Browser GPU machines
Contexts, GLSL ES shaders, textures, framebuffers, packed state, ping-pong updates, and readback form the complete machine. Each browser call stays close enough to inspect, change, and teach from first principles.
Build the browser-to-GPU path
Spatial reconfigurable architecture
Each Cartilage region owns ports, state, routing, and the path that replaces its interior. The learning path starts with Logisim and LUTs, then adds physical drive, distribution, statecharts, timing, wires, composition, and runtime installation in adjacent space.
Build the eight-stage architecture · Take Cartilage home · Open the circuit workstation · Run the public multiplier · Fund or join development
One FPGA Practice Spans Signal, Protocol, Logic, And Configuration
The same command of clocks, state, and physical pins connects radio, Ethernet, arithmetic, and runtime reconfiguration.
These systems receive and transmit RF, answer ARP in direct RTL, carry FPGA images through UDP, reprogram an adjacent iCE40, turn multiplexers into tangible tiles, and travel from Verilog through place-and-route to configured hardware. Enter the complete FPGA systems map.
RF transmit · 106 concurrent channels
The HX8K advances 106 independent 24-bit lane phases, reduces their live I/Q contributions through 254 bit-serial tree nodes, and turns the complete 4.5 MS/s complex band into four-phase RF timing on N16.
Inspect every stage and download the complete MIT-licensed transmitter
RF receive
One logical differential input thresholds RF. DDR decisions form I/Q bit lanes, DDS sign bits drive XOR mixers, and a cross product recovers FM phase motion for sigma-delta audio output.
Watch the receiver operate and read the Verilog path
Network RTL and reconfiguration
The 2020 system receives RMII, answers ARP, ingests a fixed-layout IPv4/UDP bitstream into FPGA RAM, and directly configures a neighboring iCE40LP384. Its Linux sender joins UDP, epoll, XCB, EGL, and GLES2 into the host side of the path.
Follow all 14 source files from packet to bitstream
Tangible logic for electrical engineering
PCB tiles give inputs, constants, selectors, routes, intersections, orientation, and topology a physical form that learners can assemble by hand. The system connects those pieces to Logisim, LUT1–LUT6, and FPGA logic, then carries them toward a powered teaching product.
See the assembled tiles and build the learning path
Open The Boundary That Controls The Product
Inherited stacks often hide the exact timing, state, routing, or physical constraint that decides whether a new system can exist.
Greenforest I/O turns that hidden boundary into explicit machinery: a circuit schedule, shader pipeline, reconfigurable substrate, radio path, or fabrication process that a team can inspect and extend. This work creates leverage before convention hardens into an assumed law.
Bring The Boundary Everyone Else Treats As Fixed
Strong projects include computation trapped behind a black box, arithmetic shaped incorrectly for its surrounding graph, opaque hardware/software interfaces, FPGA architectures that need a complete physical path, and process ideas that demand reasoning from physics back to working machinery.
Ways to engage: funded R&D, research architecture, product development, implementation, technical due diligence, FPGA/WebGL/semiconductor/radio collaboration, fabrication or laboratory access, and an institutional home for Cartilage and active-device development.
Research Programs And Essays Beyond Conventional Systems
Cultural critique · August 2026
Encanto Removed the Villain. Now Remove Power.
Encanto removes the villain and exposes a harder problem: love can become command. The essay follows that insight through family, school, work, human rights, refusal, and a world without masters.
We Got It All Wrong · Series premiere
The Forest And The Right To Create
One finite human life deserves tools and education that expose how creation works. Watch the first episode and read the argument for moving people from constrained consumption into authorship.
Company-scale problem map · 210 openings
210 Problems We Have Learned To Call Normal
The map connects three company-sized layers: structurally bounded authority for agents and machines, live reconfigurable physical computation, and physical intelligence built from minimal apparatus. Each layer supports a focused subsidiary and a portfolio of products.
Long-form collection · 53 essays
Miscellanies
Fifty-three finished essays develop living circuits, self-reconfiguring machines, software and communication, physical models, mind and society, language, building, learning, and creative tools.
Manufacturing program
The Missing Maker Fab
The maker loop already produces boards, enclosures, firmware, and fixtures. The missing machine fabricates active devices with nonlinear gain, restoration, fanout, interconnect, and enough repeatability for useful logic at civic scale.
Universal computing substrate
Boolean Algebra Is All That Is Required
The construction uses Boolean state and switching for application logic, ownership, configuration transport, timing, and recursive circuit replacement. MUX Algebra supplies the nested-selector derivation and all sixteen two-input functions.
Transformer training from source
Four-Layer Transformer Training Run
The complete run joins architecture, tokenizer, command, loss history, generated samples, and source through more than 50,000 training iterations.
Procedural renderer
Cheap Pixelless Textures With 2D SDFs
A self-contained scanline renderer uses UV-space signed-distance material tests and procedural geometry to construct a forest scene without ordinary bitmap texture art.
Build From The Mechanisms
Downloadable offline Cartilage authoring
Take Cartilage Home In One HTML File
Download the complete square-lattice authoring tool or the Rhombitrihex visual-language canvas, open either without an internet connection, build labeled circuits, and exchange circuit files through ordinary Open and Save controls.
Open Cartilage multiplier and private workstation
Run Cartilage In The Browser
Open the self-contained one-slot multiplier without an account, then request private access to edit, load, save, share, and follow the browser, Raspberry Pi, and FPGA streaming work.
Cartilage in browser and RTL
Cartilage Core in WebGL and SystemVerilog
Run one exact 252-bit installation through the compact WebGL1 model and local-clocked SystemVerilog RTL, then follow the architecture paper and Verilator testbench into the mechanism.
Browser GPU lineage
WebGL And Computation From First Principles
Create the context, compile the shaders, allocate textures, execute through a framebuffer, and watch state become logic and addition directly on the GPU.
Stateful local-rule machines
Cellular Automata Experiments, 2019–2021
Local rules move packed state through reversible routes, conservative dynamics, machine-like flows, and the architectural path that produced Cartilage.
Technical history
Programmable Shaders Before The GPU
RenderMan shading leads through real-time shader languages, Brook, CUDA, AlexNet, and mixed-precision matrix engines—a direct technical lineage from programmable color to AI arithmetic.
135 dated technical essays
LinkedIn Publication Index
Technical arguments, invention programs, collaboration openings, and original source records form a dated map from 2018 through 2026.