Greenforest I/O

I build the mechanisms the usual computing stack hides.

When timing, state, routing, or a physical boundary is the real problem, I reconstruct it as a runnable circuit, shader, fabric, RTL model, or test.

The result is a mechanism another engineer can run, inspect, challenge, and continue.

Streaming multiplier FPGA systems WebGL & GLSL Cartilage Work with Brian

Start With A Working Result

These are three scales of the same practice: expose the mechanism, publish the boundary, and keep the evidence next to the claim.

FPGA Systems Across Signal, Protocol, Logic, And Configuration

The FPGA work extends far beyond one arithmetic circuit.

It spans RF receive and transmit paths, Ethernet and ARP in direct RTL, network-carried images, one FPGA reprogramming an adjacent iCE40, physical MUX tiles, device primitives, timing, and open build toolchains. See the complete FPGA systems map.

Transmitter waveforms, a hand-built resonant-tank network, and historical RF spectrum context RF transmit

One-pin quadrature/SDM transmitter

The HX8K source defines two sigma-delta control paths, four-way phase selection from the source's 216 MHz quadrature carrier, and one switched RF output pin. The wrapper connects that RTL to the resonant-tank experiment while keeping fresh-build and calibrated-measurement boundaries explicit.

Inspect the transmitter

Preview for the Ethernet-to-iCE40 Verilog reprogrammer article Network RTL and reconfiguration

Ethernet to an adjacent iCE40

A 2020 source publication crosses RMII receive, ARP response, fixed-layout IPv4/UDP bitstream ingestion, FPGA RAM, and direct configuration of a neighboring iCE40LP384. The Linux sender combines UDP, epoll, XCB, EGL, and GLES2.

Inspect the 14-file source map

A palm-scale assembly of physical purple MUX, input, constant, route, and intersection PCB tiles Tangible logic for STEM EE

A physical MUX-tile alphabet

Fabricated PCB variants turn inputs, constants, selectors, routes, intersections, orientation, and topology into a language a learner can assemble and change by hand. The new project page connects the physical pieces to Logisim, LUT1–LUT6, and real FPGA logic without pretending that the prototype is already a classroom-validated powered computer.

Follow the hands-on learning path and photographic evidence

The Value I Provide

I create escape routes from inherited technical stacks.

When an implementation hides timing, state, routing, or a physical constraint that matters, I reconstruct that boundary as explicit machinery and carry it far enough for another engineer to inspect and extend. Sometimes that is a circuit schedule, sometimes a shader pipeline, sometimes a reconfigurable substrate, and sometimes a fabrication question that the normal toolchain has made invisible.

This is most useful before a team has agreed that the conventional decomposition is inevitable.

Bring A Hard Technical Boundary

Good fits include a computation trapped behind a black box, arithmetic that is the wrong shape for its surrounding graph, a hardware/software boundary that is too opaque, an FPGA or reconfigurable architecture that needs to become concrete, or a process idea that needs reasoning from physics back to runnable machinery.

Useful opportunities: funded R&D, research architecture, product development, prototype implementation, technical due diligence, FPGA/WebGL/semiconductor/radio collaboration, fabrication or lab access, and an institutional home for the Cartilage and active-device program.

Ways to work together Built evidence Send one hard boundary

Other Research And Invention

Manufacturing program The Missing Maker Fab

The maker loop reaches boards, enclosures, firmware, and fixtures, then stops at active silicon. This program asks what civic-scale process could provide nonlinear gain, restoration, fanout, interconnect, and enough repeatability for useful logic.

Substrate argument Boolean Algebra Is All That Is Required

A finite construction for using Boolean state and switching for application logic, ownership, configuration transport, timing, and recursive circuit replacement.

Learning artifact Four-Layer Transformer Training Run

The artifact keeps the architecture, tokenizer, command, loss log, generated samples, and source path together through more than 50,000 training iterations.

Procedural renderer Cheap Pixelless Textures With 2D SDFs

A self-contained scanline renderer uses UV-space signed-distance material tests and procedural geometry to construct a forest scene without ordinary bitmap texture art.

Evidence And Source Trails

Current Cartilage proof Cartilage Core in WebGL and SystemVerilog

The current package publishes the compact WebGL1 model, architecture paper, local-clocked SystemVerilog RTL, Verilator testbench, one exact 252-bit installation, and explicit non-claims.

Browser GPU lineage WebGL And Computation From First Principles

Context creation, shaders, textures, framebuffer execution, visible state, logic, and addition without a framework between the reader and the GPU.

Stateful shader machines Cellular Automata Experiments, 2019–2021

Preserved local-rule WebGL machines exploring reversible routing, conservation, packed state, and the path toward Cartilage.

Technical history Programmable Shaders Before The GPU

A sourced path from RenderMan shading through real-time shader languages, Brook, CUDA, AlexNet, and mixed-precision matrix engines, with the machines and numerical contracts kept separate.

Dated publication library LinkedIn Publication Index

Standalone technical arguments, collaboration requests, invention fragments, and source trails recovered from the feed.

Open Research That Needs Resources

Magnetics: can useful circuit behavior escape semiconductor fabrication? Learning machinery: can gradients remain visible when backpropagation is wired from primitive operations? Fabrication: can active substrates become physically reproducible at civic scale?

The maker-fab program and wafer-diced substrate note state the material boundary; serious collaborators and institutional support are welcome.