Begin Where Every Wire Is Visible
Logisim is useful here because it refuses to make the circuit disappear. A wire carries a value. A component transforms it. A clocked component holds state. You can single-step the machine and see which bit moved.
The public bubbles-free serial multiplier uses legacy Logisim 2.7.1 for exactly that reason: the streaming schedule and repeated serial-adder structure remain inspectable. The actively maintained Logisim-evolution project is a current cross-platform tool for designing and simulating digital logic. The lesson does not depend on one release. It depends on keeping the circuit concrete.
One Multiplexer Is One Address Bit
A 2:1 multiplexer has two data inputs, one select input, and one output. The select bit decides which data input reaches the output:
Y = S ? D1 : D0
Now stop treating D0 and D1 as live signals. Store two configuration bits there instead. The select input becomes an address. That is LUT1: one input chooses one of two stored truth-table values.
If the two stored bits are 1, 0, the table is an inverter. If they are 0, 1, it is a buffer. 0, 0 and 1, 1 are constant zero and constant one. The same selector implements every Boolean function of one input because the configuration supplies the function's complete truth table.
LUT2 And LUT3 Are The Same Machine Grown Outward
A LUT with N inputs stores 2^N output bits. The input vector is an address into those stored choices.
You can draw LUT2 as a two-level multiplexer tree: one select bit chooses within each pair, and the second chooses between the pair results. LUT3 adds another level. The truth-table definition is stable even when a particular FPGA implements, packs, or shares the physical resources differently.
LUT4 Is A Real iCE40 Primitive
Lattice's iCE40 technology library exposes SB_LUT4. Four inputs address a 16-bit LUT_INIT value, and the selected bit becomes the output. The official iCE40 Technology Library documents both the primitive and the input-to-LUT_INIT mapping.
This is the useful bridge from the teaching diagram to a device: LUT4 is not merely a metaphor for logic synthesis. It is a named primitive with a configuration word and an exact address convention.
LUT5 And LUT6 Are Real AMD/Xilinx Slice Modes
AMD's 7 Series and UltraScale configurable-logic documentation describes a 6-input LUT that can operate as one LUT6 output or as two LUT5 outputs with shared inputs. The current references are the 7 Series CLB overview (UG474) and the UltraScale CLB overview (UG574).
The lesson is not that every FPGA is a scaled version of iCE40. Packing, carry chains, storage, distributed RAM, routing, and slice organization differ. The lesson is that a small truth table plus physical routing is a recurring unit of real reconfigurable hardware.
Why This Is Only The Substrate
Cartilage must not be flattened into “a MUX fabric.” A lookup table explains how local Boolean choice can be configured. Cartilage adds a different architectural question: how a spatial region owns its boundary, receives a replacement image through a local reconfiguration port, composes a daughter region, and keeps configuration transport visible inside the same fabric.
That is why the learning path continues through physical gain, output drive, clock and event distribution, state machines, timing closure, metal wires, nested components, and finally runtime creation of an adjacent daughter region. The LUT is the first tile of the explanation, not the whole architecture.
Use The Chapter
- Draw one 2:1 multiplexer in Logisim and verify both select states.
- Replace its data inputs with two constants and configure inverter, buffer, zero, and one.
- Build LUT2 from three multiplexers and four stored bits.
- Encode AND, OR, XOR, and a 2:1 MUX as four-bit LUT2 truth tables.
- Compare your address order with the official
SB_LUT4LUT_INITtable before assuming bit numbering.