The Inverter Is Not An Ideal Switch
A complementary CMOS inverter uses a pull-up device and a pull-down device. With a low input, the output is driven high. With a high input, the output is driven low. Between those stable regions is a transition where the output changes sharply as the input moves.
The MIT inverter-basics lecture treats the voltage-transfer characteristic, noise margins, and sizing as the foundation of digital inverter behavior. UC Berkeley's CMOS transistors and logic lecture marks the input thresholds where the magnitude of the voltage slope reaches one.
Gain Creates Restoration
The voltage-transfer curve is steep through the transition region. In that region, a small input change produces a larger output change in the opposite direction. The magnitude of the local slope exceeds one for part of a valid digital transfer curve.
That gain is used for logic restoration, not analog fidelity: a somewhat corrupted low input produces a strong high output, and a somewhat corrupted high input produces a strong low output. A two-inverter buffer restores the original polarity while sharpening the levels. MIT's Computation Structures notes connect this greater-than-one gain region to noise margins and a valid combinational-device transfer characteristic.
This is the physical reason “0” and “1” can be compositional. Without restoring gain, noise and voltage loss accumulate until a later stage no longer knows which state it received.
Logic Also Has To Move Charge
The input gates of the next stage, the wire between stages, and the output structures all present capacitance. Changing a node voltage requires charge. A source with finite resistance takes time to deliver or remove that charge.
A first-order delay model is deliberately simple:
delay ∝ Rdriver × Cload
The exact delay of a real cell depends on the device, input slew, output load, process, voltage, temperature, interconnect, and characterization model. The useful lesson is more basic: an arrow on a logic diagram has an electrical cost, and a driver must be sized for the load it is expected to move.
Buffers Trade Area And Energy For Reach
Two inverters in series preserve polarity and form a buffer. If a small logic stage must drive a much larger capacitive load, a chain of progressively larger inverters can reduce the penalty of asking the smallest stage to charge everything directly.
This is not free. Larger devices occupy area, add their own capacitance, and consume dynamic energy when they switch. A driver chain is therefore a physical allocation decision: how much area and energy should be spent to meet a transition-time and delay budget at a particular fanout?
Output Driver Means A Boundary With A Load
“Output driver” can refer to several boundaries: a stronger internal buffer, an FPGA I/O cell, a pad driver, a board-level line driver, or another physical interface. This chapter uses the term in the general internal sense: the stage responsible for presenting a valid transition to a known load.
The distinction matters for Cartilage. A cell role can be described logically, but a clock, event, reset, configuration edge, or application signal still needs an implemented path with bounded fanout, slew, delay, and restoration. The current browser and RTL artifacts establish logical mechanisms; they do not yet establish transistor sizing or physical driver closure.
The Next Question Is Distribution
Once one driver can move one bounded load, a fabric-wide problem appears: how should one event reach hundreds or thousands of destinations without letting the nearest destination see a fundamentally different edge from the farthest one?
That is why the next chapter moves from a single transfer curve to clock, event, and reset networks—buffer trees, H-trees, grids, clock roots, leaves, and regional distribution.