One Edge, Many Arrival Times

A source sees wire capacitance, buffer inputs, register clock pins, reset pins, and other loads. The network has resistance and capacitance; buffers have delay; branches are not perfectly matched; routing detours around occupied resources; and process, voltage, and temperature shift the result.

The difference between arrival times at two destinations is skew. A clocked system must include that difference in setup and hold analysis. An event network must define whether destinations are allowed to observe different cycles. A reset network must control when state becomes active after reset is released.

Buffer Trees Bound Fanout

A tree divides one large load into smaller branches. Each buffer drives a bounded set of child buffers or leaves. The number of stages, branching factor, placement, and wire lengths determine the delay and load seen at each level.

A logically balanced tree has the same number of stages to each leaf. A physically balanced tree also tries to equalize route and load. Those are different claims: equal depth in a schematic does not guarantee equal delay after placement and routing.

H-Trees Balance Nominal Geometry

An H-tree recursively divides a rectangular region. A source enters near the center; equal-length branches reach the centers of subregions; the pattern repeats. The geometry gives selected leaves equal nominal path length.

Real loads, obstacles, wire layers, local variations, and final routing still matter. H-tree is a useful teaching shape because it makes spatial balance visible. It is not a promise of zero skew.

Grids Buy Access With Capacitance

A driven grid offers many nearby tap points and multiple paths. It can reduce sensitivity to one route and simplify local access. The price is substantial switched capacitance, metal usage, driver current, and design effort.

Trees spend less wire but depend more strongly on branch balance. Grids spend more physical resources to make distribution less tree-like. Hybrid networks use a tree or spine for long reach and local meshes or grids near the loads.

Modern FPGAs Use Dedicated Regional Clocking

AMD UltraScale devices divide the fabric into clock regions with horizontal clock spines, vertical and horizontal routing and distribution tracks, clock roots, and leaf buffers. The official Clock Structure chapter of UG572 explains how segmented resources can form device-wide or more local clock networks.

This is a better concrete reference than pretending every chip implements the three textbook shapes above. The device exposes a designed clock-distribution fabric with explicit region boundaries and routing resources. The implementation tools still have to select and place the network correctly.

Clock, Event, And Reset Are Not Interchangeable

A clock is periodic and participates directly in sequential timing. An event may be a pulse, transition, token, or locally acknowledged action. Reset establishes or restores a known state and has its own assertion and release requirements.

The physical machinery can look related—high-fanout drivers, trees, regional spines, local leaves—but the correctness conditions differ. Altera's current state-machine reset guidance gives a concrete failure mode: partial reset release can place a one-hot machine into an illegal state.

The Cartilage Question

Cartilage contains more than application data. Configuration edges, local ownership, region replacement, events, and state must also move. The architectural opportunity is to keep those paths spatial and explicit instead of assuming a hidden global control plane.

The current WebGL and RTL evidence demonstrates local configuration mechanisms on bounded examples. It does not yet close a physical clock, event, or reset network. The next conceptual step is therefore behavioral: what exactly should an event activate, and how can hierarchical behavior become visible state?