Wire Came Before Abstraction
In the 1990s, I soldered transistors and integrated circuits, drew large schematics on A1 sheets, etched printed circuit boards, and sometimes wired components directly together.
NAND gates, comparators, multiplexers, counters, and Schmitt triggers all resolved into arrangements of switches.
Programming then opened Turing machines, actors, cellular automata, lambda calculus, SKI combinators, interaction nets, processes, threads, recursion, functional programs, reactive programs, and distributed systems. The next twenty years traced the important differences among them.
Models that compute in many places and accept new arguments while earlier work remains in flight offered the richest direction. Code and data could occupy space together instead of advancing through one imagined register and source line at a time.
Each model supplies a different discipline for state, dependencies, and work. Every physical realization still moves signals, holds state, selects alternatives, and lets one event affect the next.
A Light Wand Reopened The Hardware Path
A friend moved a persistence-of-vision light wand from Raspberry Pi and Arduino into an Artix-7 FPGA to achieve tighter sensor-to-light timing. His documented Verilog supplied a direct entry point.
The same Arty board and LED strip, Vivado on Debian, and the operating design turned FPGA architecture from a concept into a machine.
The Lattice IceStick and iCE40HX1K then exposed the lower layers. Open IceStorm documentation made configuration tangible; bitstream study, place-and-route changes, iCE40LP384 parts, QFN hot-air work, and later microscope-guided iron soldering connected logic to the package.
The software reflex demanded a fast change-run-observe cycle. Ethernet on the Arty made that possible: custom ARP and UDP RTL received a new image from a laptop and programmed an adjacent iCE40. That path became the Ethernet-to-iCE40 reprogrammer.
Fifty Printed Pages Exposed Two Kinds Of Time
Roughly fifty printed pages of Verilog seemed to say everything twice. Software habits looked for calls and assignments in sequence; the circuit kept equations continuously sensitive to levels while registers accepted state on edges.
David Harel’s 1987 statecharts report and Altera’s guidance on one-hot finite-state machines made that division legible. One-hot encoding trades flip-flops for simpler decoding and transition logic, often improving timing on LUT-rich FPGA architectures.
Years of object-oriented, functional, distributed, event-driven, streaming, and domain-driven design had built strong preferences around abstraction. Hardware demanded a more physical account of when state changes and how logic between those changes settles.
Removing The Clock Leaves Physical Time Behind
Asynchronous control and hand-made edge detection exposed more timing relationships, not fewer. External inputs still changed at difficult moments, feedback still raced, and longer paths could deliver an earlier-launched signal after a later event.
The clock gave a circuit region an agreement about when state changes. A synchronous region divides the work:
- Registers hold the current state.
- Combinational logic derives candidate next state and outputs.
- Physical paths receive time to settle.
- A clock edge commits the next state together.
The clock travels through a physical distribution network and reaches different parts of the chip at different times. Data paths have minimum and maximum delays. Setup and hold requirements define the usable window around each receiving edge. Timing closure makes the local agreement true in the placed and routed circuit.
The Outer World Follows Its Own Time
A pushbutton, radio comparator, network link, sensor, or neighboring clock domain can change near a local sampling edge. The receiving flip-flop may enter metastability and take extra time to resolve—physical uncertainty in when its output becomes usable.
For one slowly changing control bit, a synchronizer chain gives the first register time to resolve before the second exposes its value to sensitive logic. Multi-bit values and streams require shared structure: handshakes, Gray-coded pointers, asynchronous FIFOs, and explicit protocols preserve relationships that independent bit synchronizers could destroy.
A clock crossing is a communication interface. Its protocol carries meaning between regions that follow different time.
The clock, event, and reset article develops the register-level pattern. The clock-region article follows the same idea into placement, skew, and timing closure.
Globally Asynchronous, Locally Synchronous
General relativity rejects one universal time coordinate, and distributed software works with variable network delay. Digital systems also benefit from timing disciplines sized to their physical regions.
Daniel Chapiro’s globally asynchronous, locally synchronous architecture gives each region an engineered clock and lets separate regions communicate through interfaces that absorb delay, buffering, and independent progress.
GALS preserves the practical value of synchronous design within each island while protocols carry causality between islands.
local state A -- protocol / buffer -- local state B
clock A clock BInside each island, timing acts as a design constraint. A protocol carries causality between islands.
Pipelines Make Reactivity Physical
A pipeline accepts a new input before the previous one reaches the end. Each stage transforms bounded state and passes a registered result onward while other stages work on different arguments.
FPGA computation feels massively parallel and naturally reactive because the structure occupies space. Registers remember progress, wiring expresses dependencies, and new values propagate without an instruction pointer polling every operator.
Datapath and control answer complementary questions. The datapath defines which values move and transform; control defines which captures, transfers, and transformations count now. Statecharts and one-hot machines clarify control while pipelined arithmetic keeps data moving continuously.
A nested hierarchy of buffered DSP pipelines can place soft custom-instruction CPU cores where sequential or irregular work fits best, then join everything through Boolean circuits and explicit protocols. Each kind of work occupies the structure that serves it without forcing every value through one instruction stream.
Finite State Eventually Returns
A maximum-length linear-feedback shift register makes the lesson visible: four flip-flops and one XOR traverse a long, apparently irregular sequence before returning to their starting state.
A single-instruction self-modifying processor made it stronger. Its complete program fit in compact RAM, which allowed exhaustive runs across the instruction combinations. However strange the intermediate behavior appeared, the complete RAM state eventually recurred.
A closed deterministic machine with finitely many states must eventually revisit one. From that point, the same future repeats. A transient may precede the cycle, the cycle may run for an extraordinary length, and an open system may keep receiving new information. The finite closed state graph still returns.
State capacity and external input therefore shape computational novelty. Long trajectories, changing environments, randomness, and new information entering through interfaces all extend what the machine can do.
Process calculi and functional reactive systems fit the same physical account. Push versus pull decides where state waits, which dependency initiates work, and how far a change travels. Boolean circuits supply decisions; stored state supplies history. An extensible supply of both lets a finite construction grow into a general computer, as the multiplexer construction develops directly.
The Clock Is A Local Treaty
The clock organizes when stored state changes. Beneath that treaty, switches, paths, delays, registers, feedback, protocols, and timing regions perform the computation.
Hand-wired gates began the path, twenty years of software abstractions expanded it, and FPGA work returned those abstractions to physical mechanisms.
Non-tail recursion stores activation state somewhere. A process communicates across an interface. A reactive dependency becomes wiring or scheduling. A concurrent pipeline occupies several places at once. An asynchronous neighbor uses a protocol. The clock orchestrates those participants without pretending to replace them.