I build complete FPGA paths across boundaries that are usually separated.
That means pin-level signal behavior, protocol parsing, clocking, arithmetic schedules, configuration transport, device primitives, open toolchains, and the Linux or browser surface used to inspect the machine.
An FPGA is not merely a place to translate software into gates. It is where electrical behavior, clocks, packet structure, state, routing, and configuration meet. I work directly at those joins.
The public record spans Lattice iCE40 and Xilinx 7-series hardware, Verilog and SystemVerilog, vendor primitives, Yosys-based toolchains, raw network framing, RF threshold crossings, and reconfiguration of one FPGA by another. The projects below are the evidence, not a generic list of skills.
RF receive
A thresholded RF stream enters one logical differential iCE40 input site. DDR decisions become I/Q bit lanes, DDS sign bits control four XOR-and-popcount terms, and a later I/Q cross product recovers FM phase movement before sigma-delta audio.
The page includes operating video, the selected UP5K source snapshot, build path, and the receiver measurements still needed.
RF transmit
The preserved iCE40 HX8K source defines two sigma-delta control paths and selects among four phases of the source's 216 MHz quadrature clock to gate one RF output pin.
The wrapper connects the RTL to the resonant-tank sketches and historical spectrum context while keeping calibrated power, spectrum, range, and a fresh build as separate evidence milestones.
Network and configuration
A 2020 multi-file source publication implements RMII receive, ARP response, fixed-layout IPv4/UDP-carried bitstream ingestion, FPGA RAM storage, and direct control of an adjacent iCE40LP384 configuration interface.
The Linux sender combines UDP, epoll, XCB, EGL, and GLES2 in the same control shell.
Arithmetic scheduling
The current Logisim artifact is an 8x8 unsigned positive-number circuit with three clocks of fixed latency and one LSB-first result bit per clock after fill. Consecutive operand words enter without a drain gap.
It is a concrete architecture for narrow streaming graphs and a clear target for an RTL port.
Tangible logic
Fabricated input, constant, selector, route, and intersection PCB variants make circuit role, orientation, and topology into objects that can be assembled and changed by hand.
The project is a physical teaching alphabet, not a claim that every assembled patch is already a powered or classroom-validated computer.
Spatial reconfiguration
Cartilage is the larger architecture: locally coherent regions of cells with owned ports, state, routing, and replacement. Its learning path runs from one MUX through LUTs, drivers, clock distribution, state, timing, metal, composition, and runtime instantiation in adjacent space.
Cartilage Core keeps the current browser and SystemVerilog proof package separate from the longer research program.
I can follow a computation until the abstraction stops matching the machine.
Sometimes the right intervention is an arithmetic schedule. Sometimes it is an FPGA input threshold used as the front edge of a receiver. Sometimes it is an ARP response and bitstream path with no CPU in the datapath. Sometimes it is a configuration port between devices, or a circuit alphabet that a learner can hold.
The value is not breadth for its own sake. It is the ability to make the boundary concrete when hardware, software, protocol, and physical behavior have been split into separate specialties.
Good work can begin with an RTL path, signal boundary, timing problem, packet interface, reconfiguration mechanism, teaching instrument, or architecture that needs to become inspectable before a team can decide what to build.