Complete FPGA systems emerge when pins, protocols, clocks, arithmetic, and configuration become one design.
This work follows each machine through pin-level signal behavior, packet parsing, clocking, arithmetic schedules, configuration transport, device primitives, open toolchains, and the Linux or browser surface that controls it.
An FPGA joins electrical behavior, clocks, packet structure, state, routing, and configuration in one programmable machine. The decisive engineering happens at those joins.
The systems here span Lattice iCE40 and Xilinx 7-series hardware, Verilog and SystemVerilog, vendor primitives, Yosys-based toolchains, raw network framing, RF threshold crossings, and direct reconfiguration of one FPGA by another.
For a first encounter with FPGAs, begin with All Things All The Time: FPGA And Verilog From First Principles. It builds upward from Boolean logic, LUTs, and flip-flops through Verilog, simulation, synthesis, placement, routing, and a programmed iCE40 board.
RF receive
A thresholded RF stream enters one logical differential iCE40 input site. DDR decisions become I/Q bit lanes, DDS sign bits control four XOR-and-popcount terms, and a later I/Q cross product recovers FM phase movement before sigma-delta audio.
Operating video, selected UP5K source, and the build path trace the receiver from a single input site to audible output.
RF transmit · 106 concurrent channels
The HX8K implements 106 independent 24-bit phase engines, deterministic FM motion, twin 128-leaf bit-serial I/Q trees, signed sigma-delta conversion, and a 7.5 MHz complex rotation before four 216 MHz phases converge on N16.
The complete SystemVerilog, support RTL, constraints, build, volatile-SRAM loader, hardware guide, and ready-to-load image are MIT licensed. Own the architecture and build it.
Network and configuration
A 2020 multi-file system receives RMII Ethernet, answers ARP, ingests a fixed-layout bitstream through IPv4/UDP, stores it in FPGA RAM, and controls an adjacent iCE40LP384 configuration interface directly.
The Linux sender combines UDP, epoll, XCB, EGL, and GLES2 in one control shell.
Arithmetic scheduling
The SystemVerilog core produces one low 64-bit product every 64 clocks at 216 MHz: 3.375 million products per second from 254 LUT4s and 635 flip-flops.
Twelve independent cores fit the HX8K and deliver 40.5 million products per second. The article publishes the RTL, build, utilization, host verifier, and physical run data.
Binary32 arithmetic
Raw IEEE binary32 words cross the boundary LSB first while significands, exponents, and signs move through one-bit internal streams. A 216 MHz HX8K accepts a new finite-normal division every 32 clocks.
Three serial multipliers, eight add/subtract engines, and three comparators turn the continuous schedule into 6.75 million correctly rounded finite-normal divisions per second, with open RTL and complete rebuild files.
Tangible logic
Input, constant, selector, route, and intersection PCB variants turn circuit role, orientation, and topology into objects that learners can assemble and change by hand.
This physical teaching alphabet carries the logic of MUXes and LUTs out of diagrams and into palm-scale compositions.
Spatial reconfiguration
Cartilage organizes cells into locally coherent regions with owned ports, state, routing, and replacement. Its learning path runs from one MUX through LUTs, drivers, clock distribution, state, timing, metal, composition, and runtime instantiation in adjacent space.
Run Cartilage Core, then follow the editor, simulator, ownership, and recovery roadmap. The architecture invites funding, implementation partners, and contributors.
The useful abstraction ends where it stops matching the machine.
The right intervention may take the form of an arithmetic schedule, an FPGA input threshold at the front of a receiver, an ARP response and bitstream path with no CPU in the datapath, a configuration port between devices, or a circuit alphabet that a learner can hold.
That cross-layer range turns hardware, software, protocols, and physical behavior back into one tractable system—the point where difficult product and research problems often yield.
Start with an RTL path, signal interface, timing problem, packet boundary, reconfiguration mechanism, teaching instrument, or architecture. Together, we can turn it into a machine that a team can run, inspect, and develop.