Serial is not automatically inferior when the schedule remains full.

A positive-number bit-serial multiplier whose schedule stays full: after startup alignment, each clock advances the next input bits and emits the next product bit, with no drain cycles between operand words.

The public artifact is a Logisim circuit. The rendered version is 8x8 bits with an 8-bit result stream. The width can be changed by building a wider version of the same pattern; the point of this article is the schedule.

Circuit artifactThis page delivers the Logisim circuit, rendered schematics, streaming schedule, and current implementation scope.

Included: the bubbles-free streaming schedule, LSB-first streams, 8x8 to 8-bit rendered circuit, 3-clock fixed latency in the rendered example, serial adders, Logisim file, and circuit images.

Article focus: positive-number arithmetic in the current Logisim artifact: 8x8 input streams, 8-bit output stream, LSB-first timing, 3-clock fixed latency in the rendered example, and one output bit per clock after fill.

Why It Exists

The circuit was invented on July 26, 2025 because ordinary FPGA multiplication was becoming the wrong shape for the intended compute graph. A standard Verilog * was pushing timing closure too slowly, hard multiplier blocks were scarce, and the design needed a streamable arithmetic path instead of another wide immediate product.

This multiplier keeps arithmetic in a narrow, regular, bit-serial stream. Every word advances on the same cadence, and the pipeline does not need a bubble between consecutive operands.

What Exists

The source is serial_july_2025.circ, a Logisim 2.7.1 project. The rendered multiplier image is mul.png, and the rendered serial adder image is add.png.

The reusable circuits in the file include var, add, mul, and helper harnesses. The article is about mul, with var as the serializer and add as the clocked serial adder used inside the reduction tree.

Streaming Behavior

The input streams are LSB-first. The output stream is also LSB-first. In the rendered 8-bit circuit, the fixed pipeline latency is 3 clocks, matching the depth of the balanced serial reduction tree. Once that latency is accounted for, output bits continue one per clock.

"Bubbles-free" means there is no idle drain period between words. The next operand word begins immediately after the previous operand word in the same stream cadence. The output side behaves the same way: after the fixed latency, result bits keep coming on every clock.

There is no reset/start framing between words and no ready/valid backpressure in this artifact. The stream phase begins from power-on, and the surrounding circuit must know which clock corresponds to bit 0 of each word.

Schematic Anatomy

The important pieces are compact:

var serializes an 8-bit value into a one-bit stream.
add is the clocked serial adder and carries the serial carry state.
mul generates partial-product lanes and reduces them through a balanced tree of serial adders.
dbg, main, and main2 are inspection and harness support.

Partial products are not stored as a wide parallel matrix. They exist as delayed and gated bit streams feeding the serial reduction tree. Carry propagation is handled inside the clocked serial adders instead of through one wide carry chain across a parallel product bus.

Scaling

The design scales linearly in resources with the number of input bits. Wider versions add repeated lanes and reduction structure instead of a wide parallel multiplier block. In the balanced serial reduction tree, doubling operand width adds one clock of extra tree latency.

The rendered artifact is 8x8 to 8 bits: the result stream is intentionally cut to 8 bits. A different output width would be a deliberate variant of the same schedule, not a different claim in this article.

Why This Shape

The cost is not simply "serial is slower." The architecture replaces wide immediate products with a uniform streaming schedule, narrow local links, and graph-style composition. That is the engineering value in this artifact.

Hard multiplier blocks and inferred * multipliers remain useful. This circuit explores the opposite direction: keep multiplication in the same bit-stream rhythm as the surrounding arithmetic and make the schedule easy to compose.

Artifacts

Logisim circuit file Logisim serial adder circuit

Serial adder image

These are the current public artifacts: the Logisim circuit and rendered circuit images.

Next Measurement

The useful next comparison is a Verilog implementation measured on the same FPGA target against inferred * and hard-multiplier implementations: LUT count, Fmax, timing report, waveform capture, and placement behavior.