Cartilage Core: Reconfigurable Fabric in WebGL and SystemVerilog

A child-owned port receives 252 bits and transforms a 6x6 region into an AND circuit.

Cartilage Core implements the same nearest-neighbor reconfigurable fabric in WebGL1 and SystemVerilog. Local state, routing, ownership, and configuration remain visible all the way from the serial image to the operating circuit.

Revision b5bd1c0 carries the browser machine, local-clocked RTL, self-checking Verilator testbench, architecture paper, capture tools, and exact 36-record installation.

Run the public source Read the hardware paper Follow the RTL Run the testbench

Watch A Region Become A Circuit

Cartilage Core browser fabric installing a 252-bit configuration into a purple 6 by 6 child-owned region and settling to an AND circuit — The browser model delivers 252 payload bits to a 36-cell region, applies the image, and completes with `A=1`, `B=1`, `Y=1`.

The final PNG shows the installed state. The capture sidecar records the source hash, browser version, frame and state hashes, exact dimensions, and final machine state. Capture provenance and file hashes connect every image back to its run.

Browser State And Hardware Timing Meet

The browser model exposes finite packed state, local transitions, an ownership tree, the serial stream, and the installed result behind Boolean Algebra Is All That Is Required. The SystemVerilog implementation gives the application plane continuous combinational behavior while locally routed reconfiguration-clock edges control installation.

The WebGL host advances a ping-pong texture simulation and compares the previous modeled clock state. The RTL realizes positive and negative local configuration edges, a three-bit route-shadow handoff, and a fabric with no global application-clock port.

Together, the two implementations separate spatial computation from host stepping and make the configuration mechanism concrete in both software-visible and hardware-native forms.

The Mechanism

Each installed record has seven bits: two orientation bits, three mode bits, and two parent-direction bits. The 6x6 example has 36 records:

36 records x 7 bits = 252 payload bits
252 payload bits + 1 apply pulse = one complete installation

The installer traverses the ownership tree in postorder, so descendants receive their records before the root. The region owns the port that configures it; when the root record arrives last, it replaces that port role with ordinary application logic. The image uses an interior MUX and constants to realize AND.

MUX Algebra shows why that selector-plus-constants construction realizes AND and how the same local choice form covers the other 15 two-input Boolean functions.

Root-port replacement completes the act of installation: the entry point disappears into the circuit it created. Relocating the next port can extend the same principle into repeated spatial growth.

The Same Architecture Across Four Surfaces

Browser model

Single-file WebGL1 fabric with 32 by 64 cells, two RGBA8 texels per cell, a 6 by 6 ownership tree, a region API, and the visible 252-bit install.

Browser verifier

Structural and functional checks exercise offline operation, local GLSL reads, ownership, primitive roles, configuration behavior, exact records, and all four AND rows.

SystemVerilog RTL

Application, router, cell, fabric, and package modules with continuous application behavior and local routed configuration clocks.

RTL testbench

Self-checking Verilator testbench: 410 primitive vectors, rotated ports and priorities, local edges, route shadow, all 36 installed records, and four AND rows.

Architecture

Editable hardware paper and rendered PDF connect the local roles, ownership, configuration stream, and Boolean-complete basis.

A Clean Clone Rebuilds The Machine

Revision b5bd1c0 completes npm ci, npm run rtl:test, the paper build, and the documented capture command from a clean clone. The RTL testbench passes 410 primitive vectors, port rotations and priorities, local configuration edges, route-shadow transfer, all 36 records, and the four AND truth-table rows.

Nine browser structural and functional checks cover offline operation, local reads, ownership, primitive roles, installation, exact records, and circuit output. The capture tool binds the visible result to source, browser, frame, and state hashes.

One repository repair will make the browser suite one-command clean: npm test returns nonzero because its compactness comparison requests a source-baseline ref that GitHub does not publish. Publishing that ref or pointing the comparison at a published baseline will let the top-level command report the nine passing checks directly.

The Core Opens A Product Path

Local role functions, routed child ownership, local configuration edges, exact serial installation, route-shadow handoff, and the operating AND circuit form a compact substrate for spatial reconfiguration.

The next engineering layers can add synthesis targets, timing and physical characterization, an application DFF role, feedback semantics, autonomous ownership discovery, and a placer/router that compiles larger circuit graphs into installed regions.

Those layers point toward a visual workstation where a designer can draw a computation, place it into live fabric, inspect its local state, recover damaged regions, and move the same design between a browser model and hardware.

From A Large Visual Field To A Compact Core

Cartilage Core descends directly from cartilage26/cartilage3.html at source revision 4143b8a, which also produced the Cartilage 2026 450-frame sequence. The compact core isolates the configuration and application mechanisms so engineers can carry them into RTL.

The 2021 WebGL machines and later QuadFlow/QFG runs show other scales and spatial arrangements in the same lineage. The physical MUX and wire tile alphabet carries the readable roles into connectorized PCB parts that people can arrange by hand.