Cartilage now has an inspectable mechanism package, not only a visual argument.

Cartilage Core publishes a compact nearest-neighbor fabric, its hardware model, the configuration protocol, and executable checks. A child-owned port receives a complete 6x6 image as 252 payload bits plus one apply pulse. The installed image then uses an interior MUX as an AND circuit.

Audited revisionb5bd1c0, July 10, 2026.

Established: a Boolean-complete local role basis, child-owned postorder configuration, an exact 36-record installation, local configuration edges in RTL, and all four AND truth-table rows.

Boundary: executable logical evidence, not silicon signoff or a general placer/router.

View public source Read hardware paper Inspect RTL Inspect testbench

The Captured Installation

Cartilage Core browser fabric installing a 252-bit configuration into a purple 6 by 6 child-owned region and settling to an AND circuit — A native-pixel capture from the audited browser model. The 36-cell region receives 252 payload bits and completes with `A=1`, `B=1`, `Y=1`.

The late PNG preserves the completed visible state. The capture sidecar records the source hash, browser version, frame and state hashes, exact capture dimensions, and final machine status. Capture provenance and file hashes are published beside them.

What This Changes

The implementation evidence accompanying Boolean Algebra Is All That Is Required is no longer limited to a browser shader. The browser model still shows the finite packed state, local transition, ownership tree, serial stream, and visible installed result. The new SystemVerilog layer independently makes the application plane continuous and combinational while configuration changes occur only on locally routed reconfiguration-clock edges.

That distinction matters. The WebGL host advances a ping-pong texture simulation and compares the previous modeled clock state. It is evidence for the modeled behavior, not a physical clock implementation. The RTL separately checks positive and negative local configuration edges, the three-bit route-shadow handoff, and a fabric with no global application-clock port.

The repository therefore strengthens the concrete construction beneath the paper. It does not by itself prove every premise used by the theorem.

The Mechanism

Each installed record has seven bits: two orientation bits, three mode bits, and two parent-direction bits. The 6x6 example has 36 records:

36 records x 7 bits = 252 payload bits
252 payload bits + 1 apply pulse = one complete installation

The ownership tree is traversed in postorder. Descendants receive their records before the root. The port is owned by the region it configures, so the root record arrives last and replaces the port role with ordinary application logic. The checked image uses an interior MUX and constants to realize AND.

The example proves that root-port replacement. It does not yet relocate a new port and perform a second full installation through that relocated ingress.

Evidence Layers

Browser model

Single-file WebGL1 fabric, 32 by 64 cells, two RGBA8 texels per cell, 6 by 6 ownership tree, boundary API, and visible 252-bit install.

Browser verifier

Structural and functional checks for offline operation, local GLSL reads, ownership, primitive roles, configuration behavior, exact records, and four AND rows.

SystemVerilog RTL

Application, router, cell, fabric, and package modules with continuous application behavior and local routed configuration clocks.

RTL testbench

Self-checking Verilator evidence: 410 primitive vectors, rotated ports and priorities, local edges, route shadow, all 36 installed records, and four AND rows.

Design contract

Editable architecture paper and rendered PDF, including what has and has not been established.

Fresh-Clone Check

I audited the public repository at b5bd1c0. From a clean clone, npm ci, npm run rtl:test, the paper build, and the documented capture command completed. The RTL run passed its advertised checks.

The browser command deserves a precise caveat: its other nine structural and functional tests pass, but npm test currently exits nonzero because one compactness comparison names a source-baseline ref that is not published on GitHub. The repository currently exposes only main. That publication defect is separate from those results, but the top-level browser suite should not be called green until the ref or the test is repaired.

Established And Not Established

The package establishes the logical mechanism for this particular image: local role functions, routed child ownership, local configuration edges, exact serial installation, route-shadow handoff, and the checked AND circuit.

It does not establish fabricated silicon, synthesis or place-and-route results, timing, area, frequency, power, metastability behavior, physical generated-clock closure, gate-level extracted-delay behavior, formal placed-netlist equivalence, a general placer/router, arbitrary feedback semantics, an application DFF opcode, or autonomous ownership discovery.

The public repository also has no published license, release, hosted live demo, or GitHub Actions record. It is accurate to call it public source and executable evidence; it is not yet accurate to assign a reuse license or call the results CI-proven.

Lineage

Cartilage Core was reduced directly from cartilage26/cartilage3.html at source revision 4143b8a, the same revision used for the Cartilage 2026 450-frame packet. It is the current compact descendant of that artifact.

The repository is not the historical source tree for the preserved 2021 WebGL demos or the later QuadFlow/QFG captures. Those older artifacts remain evidence of their own runs and should be read through their wrappers.