Ownership became visible enough here to show square child regions and active port roots inside a running fabric.

This is a preserved Cartilage WebGL/GPGPU visual milestone: a self-contained renderer where reconfiguration-port roots belong to the child subtree, while the initialized ownership tree remains a square 6x6 block.

The artifact is not a hand-drawn diagram. The GIF is captured from the running GLSL fabric, and the runnable demo is copied as a standalone web page.

Live milestoneThis page delivers the checked boot/preallocation and render-capture milestone.

Included: child-owned reconfiguration port roots, square 6x6 ownership blocks, active port-root initialization, the 252-bit transaction calculation, and the 450-frame capture.

Milestone focus: child-side reconfiguration ports, visible ownership blocks, local port roots, and the WebGL/GPGPU render path for this 2026 fabric step.

The Captured Artifact

Cartilage 2026 WebGL fabric showing active child-owned reconfiguration port roots and square ownership blocks — Cartilage 2026 fabric evolution captured from the WebGL/GPGPU renderer. The image is a native top-left crop from a 1024x2048 render, not a resized render.

Open the Cartilage 2026 WebGL artifact

The Run Package

The published packet contains the standalone WebGL artifact, the 450-frame GIF capture, a technical README, and a verification report for the boot ownership shape.

Runnable artifact: cellular-automata-2019/cartilage2026.html

Captured render: cartilage3-active-port-roots-450f-512x1024.gif

Technical handoff: cartilage2026/README.md

Verification report: cartilage2026/verification-report.md

The source snapshot, copied file hash, GIF hash, timing calculation, and explicit non-claims are documented in those packet files.

Current core referenceCartilage Core is now the compact source-and-hardware entry point.

Its public source repository adds a single-file WebGL1 model, architecture paper and PDF, local-clocked SystemVerilog RTL, and a self-checking Verilator testbench. It proves an exact 252-bit 6x6 installation plus one apply pulse and all four rows of an interior-MUX AND circuit.

Lineage: Cartilage Core was reduced directly from the same cartilage26/cartilage3.html source revision, 4143b8a, that produced this 450-frame packet. It is the compact descendant; this page's packet remains authoritative for the capture itself.

The Engineering Claim

The current milestone changes the ownership model around reconfiguration ports. A reconfiguration port is treated as the root of the child subtree. The port's parent direction selects the external application ingress side, while the child subtree still uses ordinary square ownership parent pointers.

That distinction matters because the port role can be physically shifted without collapsing the initialized ownership shape. The role column and the ownership tree are related, but they are not the same data structure.

What The GIF Shows

The visible fabric is a 32x64 logical-cell WebGL/GPGPU renderer. Each logical cell uses two RGBA texels of state. The full native render is 1024x2048; the GIF is the native top-left 512x1024 crop.

The focus is the initialized reconfiguration corridor and preallocated square blocks. The corrected boot shape restores every cell of each square 6x6 block instead of letting the visible ownership structure collapse into a short row near the reconfiguration port.

The Bug And The Fix

The difficult part was not merely shifting the port/wire role columns. The ownership tree also had to be restored as full square 6x6 subtrees by writing all 36 parent pointers at boot.

One subtle startup bug remained after that: shifted port root cells were initialized without an explicit active configuration signal. Because the engine has a parent-rotation fallback when conf_signal is inactive, child pointers near an inactive port root could rotate during the first compute steps.

The final fix initializes those shifted port roots with conf_signal: 1.0. That keeps the child-owned square subtree active from the first frame.

Transaction Size And Timing

A complete square 6x6 transaction is 36 cell records. Each record is seven bits: two orientation bits, three mode bits, and two parent-direction bits.

36 cells * 7 bits = 252 bits

The current renderer advances COMPUTE_STEPS = 30 updates per rendered frame. The internal configuration clock toggles every 25 GPGPU updates, so one complete clock cycle is 50 updates.

252 * 50 / 30 = 420 rendered frames

The included capture records 450 frames so the block fill and a short post-fill tail are visible.

Verification Boundary

The packet verifies the boot/preallocation state and included render capture. Static checks confirmed that the square slot grid contains every slot 0..35 exactly once, both ownership templates contain 36 records, the active bitstream is 252 bits, and no old root-append workaround remains.

The byte-level start-state check decoded the initialized first 6x6 block and confirmed the expected parent-direction grid plus active conf_signal bits in all 36 cells.

This does not claim readout is implemented. It does not claim the fabric is a finished 4x4 coarse reconfiguration model. It does not claim that every future dynamic reconfiguration stream has been exhaustively verified.

How To Read It

Use the Cartilage Visual Language article for the 32-code body-role alphabet: reconfiguration port, cross, constants, wire orientations, and MUX modes.

Use the earlier Cartilage nested-instantiation demo article for the broader parent/daughter-region model. This 2026 artifact is a more recent boot-shape and reconfiguration-port-root milestone in that same line of work.

Ownership Boundary

The useful distinction is between role column, parent pointer, and active configuration wire. If those three fields collapse into one visual idea, the render stops explaining child-owned reconfiguration ports.