All Things, All The Time: FPGA And Verilog From First Principles

July 23, 2026

Seven chapters ยท one circuit from logic to pins

An FPGA gives every logic function, register, and route a physical place where it can operate at the same time.

Begin with Boolean functions and clocked state. Enter the LUT-and-routing fabric. Write Verilog, drive it with a self-checking testbench, inspect its waveform, assign board pins, and carry the circuit through synthesis, place-and-route, bitstream packing, and an iCE40 board.

Each chapter adds one concrete object to the same machine: LUT, flip-flop, toolchain, source hierarchy, counter, constraint, routed configuration, and visible board output.

Begin chapter 1 Set up the workbench Build the counter
Seven-step FPGA and Verilog course map from the FPGA mental model through a programmed physical board
Seven steps move one digital idea from an FPGA mental model to a configured physical board.

Build One Complete Path From Logic To Pins

Chapter 1

What An FPGA Is

Contrast ASIC geometry with FPGA configuration, then connect concurrent Boolean logic to state that advances at clock edges.

Chapter 2

Inside An FPGA

Trace a signal through LUTs, flip-flops, local switchboxes, long routes, memories, DSP blocks, clocks, and I/O cells.

Chapter 3

An FPGA Learning Roadmap

Move from Boolean logic and Logisim into HDL, simulation, board I/O, CMOS depth, and ASIC implementation in a useful order.

Chapter 4

Build A Complete Verilog Workbench

Install Icarus and GTKWave, run the included counter testbench, inspect its VCD waveform, and bring in Verilator for C++ integration.

Chapter 5

Anatomy Of A Verilog Project

Connect source files, module hierarchy, the selected top, the design under test, timed stimulus, executable checks, and board constraints.

Chapter 6

Recreate A CD4029B Counter

Turn the CD4029B datasheet into executable counter behavior with load, direction, binary/decade modes, wrap, carry, and cascade.

Chapter 7

Put Verilog On An FPGA

Use Yosys, nextpnr, IceStorm, and the Alchitry loader to turn Verilog, constraints, and a selected board revision into a visible LED sequence.

Finish With Four Durable Capabilities

Circuit model
Distinguish source code, concurrent logic, stored state, a technology-mapped netlist, routing, and configuration
Simulation result
Run a self-checking counter testbench and inspect its VCD waveform in GTKWave
Implementation chain
Follow iCE40 Verilog through Yosys JSON, nextpnr ASC, IceStorm BIN, and the board loader
Spatial next step
Use the conventional FPGA foundation to enter the separate Cartilage learning path and understand its locally coherent regions on their own terms

Make Every Tool Advance the Same Circuit

Simulation makes behavior executable. The testbench drives inputs, clocks time, checks outputs, and records transitions. Implementation then assigns package pins, maps device resources, routes signals, and analyzes timing. The board turns the configured circuit into a visible physical result.

Analogies open the door; hardware structure carries the lesson. SQL, publish/subscribe, software I/O, an Arduino loop, and reactive programming each illuminate one aspect of HDL. Verilog describes concurrent hardware processes, while statements inside each procedural block still follow the language's ordering rules.

Carry the Conventional Flow Into New Architectures

The seven chapters establish the vocabulary that every programmable fabric must answer: logic, state, placement, routing, timing, configuration, I/O, and observation.

That foundation makes the transition to Cartilage productive. Conventional FPGA tools place a design into a vendor fabric; Cartilage explores locally coherent spatial regions, visible routes, and runtime replacement from another architectural direction.