What An FPGA Is: ASICs, Bitstreams, Logic, And State

Begin With The Silicon, Not The Acronym

Most modern electronic functions are implemented by integrated circuits cut from processed semiconductor wafers. A fabrication plant—the fab—forms devices and patterned interconnect through repeated deposition, lithography, etching, implantation, and related process steps. Those physical structures do not rearrange themselves when the finished chip is powered.

An integrated circuit is the broad category. An application-specific integrated circuit, or ASIC, is designed for a particular application or family of applications. A microprocessor or GPU is an integrated circuit, but calling every chip an ASIC erases useful distinctions. An FPGA is also an integrated circuit. What makes it unusual is not a different substance; it is the configurable architecture built into the silicon.

Ross Freeman, a Xilinx cofounder, is credited with the FPGA concept, and the Xilinx XC2064 arrived in 1985 as the first commercial FPGA. “Field-programmable” means that a user can choose the device’s configured function after manufacture—at a lab bench, in a product, or even while a larger system is deployed.

Hard-Wired In The Fab

The original manuscript’s phrase is worth keeping: ASICs are hard-wired in the fab. For a digital ASIC, an engineer may begin with Verilog or VHDL, but the path does not jump directly from source code to transistors. Synthesis produces a technology-mapped netlist; physical design establishes the floorplan and power network, places cells, builds clock trees, routes signals, and closes timing and physical-verification requirements. Signoff data—often GDSII or OASIS—describes geometry used to make masks for the selected manufacturing process.

Three terms must stay separate:

Modern process access varies by foundry, node, program, and agreement; it is not governed by one universal “everything below 130 nm is secret” rule. The open SkyWater SKY130 PDK documentation is the public 130 nm reference the manuscript was reaching for. A PDK is not itself a standard-cell library, and an educational shuttle program is not a promise of one free tapeout on a fixed annual schedule.

Soft-Wired In The Field

The companion phrase is also worth keeping: FPGAs are soft-wired in the field. Verilog or VHDL again describes desired hardware. Synthesis maps that design to the FPGA family’s available primitives; place-and-route selects particular sites and interconnect; a bitstream records the configuration choices.

Loading a new bitstream does not manufacture new transistors. It changes values held in configuration memory or related programmable elements. Those values control lookup-table contents, routing switches, I/O modes, clock resources, embedded memories, arithmetic blocks, and other features already built into the device.

That distinction explains the FPGA’s experimental power. An ASIC mask commitment is expensive and slow to reverse. An FPGA can usually receive another configuration many times, often in milliseconds to seconds depending on device, image size, and configuration interface. Some systems let one FPGA load another. The site’s Ethernet-to-adjacent-iCE40 project is a concrete example: network data is received, stored, and used to drive another FPGA’s configuration pins.

The Circuit Is Many Boolean Functions At Once

A software developer often meets a machine as a stream of instructions executed by one or more processor cores. An FPGA invites another view: a spatial network of Boolean functions, storage elements, memories, arithmetic blocks, and wires that operate concurrently.

The manuscript described a “forest” of Boolean-function trees whose branches must be shared. That image captures something important. A useful digital design cannot expand every expression into an independent truth table of all possible inputs; the resource count would grow exponentially. Real designs name and reuse intermediate results, register boundaries, buses, memory, hierarchy, and specialized blocks. Synthesis turns that shared logical graph into resources the target device can actually supply.

Each combinational output is still only a value—a bit or a vector of bits—computed from current inputs and current state. To make a machine that unfolds through time, the design needs storage.

A D Flip-Flop Separates Now From Next

A positive-edge-triggered D flip-flop samples the value on D when its clock makes the specified transition, then holds that sampled value on Q until a later active edge or control event. That behavioral contract is the portable idea. A particular transistor implementation may use latches, transmission gates, multiplexers, or other structures, so “every D flip-flop is an internal double buffer” is too specific to serve as the definition.

For synchronous design, the clean mental model is:

1. Current register outputs and external inputs feed combinational logic.
2. The combinational network computes candidate next values.
3. At the active clock edge, receiving flip-flops capture those values.
4. The newly stored values become current state for the following cycle.

This is the “old value / new value” insight in the manuscript, made precise. The old state remains observable before the edge; the next-state equations are evaluated from it; the edge commits the next state. A nonblocking assignment in clocked Verilog is designed to express that pattern.

“Massively Parallel Reactive Programming” Is A Bridge

Calling FPGA work massively parallel reactive programming can help a software developer cross the first conceptual gap. Many hardware processes respond to input and state changes, and physically distinct resources can operate during the same clock interval. A processor generally time-multiplexes a smaller number of execution units among many software operations.

But the analogy must not become a false limit. Modern CPUs contain multiple cores, pipelines, SIMD units, caches, accelerators, and asynchronous I/O; they do not literally move only one value at a time. Reactive software is neither impossible nor inherently impractical. The FPGA advantage appears when the desired computation benefits from deterministic spatial pipelines, unusual word widths, many simultaneous I/O lanes, cycle-level timing, or a datapath that does not fit a processor’s instruction machinery.

Likewise, Verilog is not simply a software reactive framework. Modules and processes exist concurrently, continuous assignments react to their dependencies, and statements inside a procedural block follow the language’s execution semantics. The next chapters replace the analogy with the actual fabric.