Finite State Is Stored Behavior
A combinational circuit maps present inputs to outputs. A finite-state machine also remembers a current state. Inputs and current state determine outputs and the next state; a clock or event commits that next state.
The diagram is not the machine. The machine needs storage bits, transition logic, output logic, a clock or event discipline, reset behavior, and routes between them. The value of a state model is that it makes those behavioral obligations explicit before physical implementation.
Harel Added Depth And Concurrency
David Harel's 1987 paper, “Statecharts: A Visual Formalism for Complex Systems”, extends conventional state diagrams with hierarchy, orthogonal components, and broadcast communication.
Hierarchy lets a transition target a containing state instead of repeating the same transition from every substate. Orthogonal regions describe activities that are simultaneously active. Events coordinate transitions without flattening the whole behavior into one enormous state list.
Those features matter for nested machinery. A daughter component can have internal states while the parent sees a higher-level mode. A configuration event can affect one region without pretending the entire fabric is one flat controller.
One-Hot Encoding Makes State Spatial
In one-hot encoding, a machine with four states uses four state bits. Exactly one is asserted during valid operation:
IDLE=0001 · RECEIVE=0010 · APPLY=0100 · RUN=1000
AMD's Vivado synthesis guide describes one flip-flop per state and one asserted state bit per cycle. Current tools can choose among one-hot, sequential, Gray, Johnson, and other encodings; one-hot is a design choice, not a universal optimum.
The spatial advantage is directness. Each state has a named storage location. Transition logic can often test one state bit instead of decoding a dense binary code. The cost is more storage bits, plus the need to handle invalid zero-hot or multi-hot states.
A Concrete Teaching Machine
Consider a simplified region installer:
- IDLE: wait for a request.
- RECEIVE: accept configuration bits and track completion.
- APPLY: commit the received image at a defined boundary.
- RUN: expose the installed application's behavior.
The RECEIVE state can contain substates for bit transfer and completion. A larger machine can run application behavior in one orthogonal region while configuration transport advances in another, if the architecture defines how those activities interact.
This sequence resembles the concerns visible in Cartilage Core's bounded installation, but the diagram above is intentionally pedagogical. It does not claim that the current browser model or RTL is implemented as this exact four-state controller.
Reset Is Part Of The Encoding
A one-hot machine is invalid if no state bit or multiple state bits are active. Reset must establish one legal starting state, and reset release must not let only part of the state register advance.
AMD exposes FSM_SAFE_STATE options for detecting invalid states and returning to a specified valid state. That is one tool-specific mechanism. The architectural lesson is that recovery behavior must be designed; “one-hot” alone does not make illegal states impossible.
From Behavior To Placement
Once each state and event has storage and logic, physical questions return. Which clock region contains the state bits? How far does an event travel? What is the longest transition path? Does a hierarchical boundary also become a placement boundary? Which wires carry a state transition across the region?
The next chapter treats clock regions and timing closure as part of the architecture rather than as a report generated after the interesting work is over.