Turn Behavior Into Stored State And Transitions
A combinational circuit maps present inputs to outputs. A finite-state machine also retains a current state. Inputs and current state determine outputs and the next state, while a clock or event commits the transition.
The machine combines storage bits, transition logic, output logic, a clock or event discipline, reset behavior, and routes between them. A state model makes every behavioral obligation explicit before physical implementation begins.
Add Hierarchy, Concurrency, And Broadcast Events
David Harel’s 1987 paper, “Statecharts: A Visual Formalism for Complex Systems”, extends conventional state diagrams with hierarchy, orthogonal components, and broadcast communication.
Hierarchy lets one transition target a containing state instead of repeating that transition from every substate. Orthogonal regions express simultaneous activity. Events coordinate transitions while preserving the behavior’s nested structure.
Those mechanisms fit nested machinery directly. A daughter component can manage internal states while its parent observes a higher-level mode, and a configuration event can act on one region inside a larger fabric.
Give Every State A Visible Storage Location
One-hot encoding maps four states onto four state bits. Valid operation asserts exactly one bit:
IDLE=0001 · RECEIVE=0010 · APPLY=0100 · RUN=1000
AMD’s Vivado synthesis guide describes one flip-flop per state and one active state bit per cycle. Current tools also offer sequential, Gray, Johnson, and other encodings; designers choose one-hot when its direct state decoding and placement properties fit the machine.
Each state occupies a named storage location, and transition logic can test one state bit instead of decoding a dense binary code. The encoding spends more storage bits and requires explicit recovery for zero-hot or multi-hot patterns.
Drive A Four-State Region Installer
A compact installation sequence assigns one visible job to each state:
- IDLE: holds the machine until a request arrives.
- RECEIVE: accepts configuration bits and tracks completion.
- APPLY: commits the received image at a defined boundary.
- RUN: exposes the installed application’s behavior.
RECEIVE can contain substates for bit transfer and completion. A larger statechart can run application behavior in one orthogonal region while configuration transport advances in another under an explicit interaction protocol.
The four-state abstraction isolates the same installation concerns that Cartilage Core handles across its bounded browser and RTL mechanisms.
Make Reset And Recovery Part Of The Encoding
Zero active bits and multiple active bits both violate a one-hot encoding. Reset establishes one legal starting state, and coordinated release keeps the entire state register on the same transition.
AMD exposes FSM_SAFE_STATE options that detect invalid states and return to a specified valid state. This tool-specific mechanism illustrates the architectural requirement: explicit recovery completes the encoding.
Place The Behavior Into A Physical Region
Every state and event now has storage and logic, so placement determines which clock region contains the bits, how far events travel, which transition path dominates, where hierarchy becomes a placement boundary, and which wires cross that boundary.
The next chapter turns clock regions and timing closure into architectural design work.