Interconnect Has A Stack
Integrated circuits use multiple conducting layers separated by dielectric. Design rules define widths, spacings, enclosures, pitches, allowed directions, and via structures. A route moves along one layer, changes layers through a via, and eventually reaches a pin shape on a cell or macro.
Different layers can be assigned different preferred directions and different roles. A flow may reserve a layer range for signals and another for clocks. OpenROAD's global-routing documentation exposes separate signal and clock layer ranges and layer-by-layer capacity adjustments.
Resistance And Capacitance Make Delay Spatial
A metal segment has resistance along its length and capacitance to neighboring conductors and the substrate. Vias add resistance and geometry. The driver must charge or discharge the combined wire and input capacitance.
OpenROAD's parasitics-estimation reference lets a flow set resistance and capacitance by routing layer, distinguish clock and signal wire models, and estimate parasitics from placement or global routing. The important transition is from “net A connects to B” to “this route through these layers has an estimated physical cost.”
Capacity Makes Routes Compete
A layer contains a finite number of legal tracks. Pins, macros, power structures, blockages, and already-routed nets consume access and capacity. When too many desired routes cross one area, the router detours, changes layers, adds vias, or fails to find a legal solution.
That is congestion. It is why the shortest abstract connection may become a long physical route, and why placement, floorplanning, hierarchy, and high-fanout structure can determine timing before a single gate delay changes.
Cartilage Side-Metals Are A Logical Substrate
The preserved cartilage3 substrate gives each square cell three incoming and three outgoing directional connections on each of four sides—24 edge “metals” per cell, excluding power. Sixteen belong to the Sinew reconfiguration overlay; eight carry application or intersection state.
In the WebGL artifact, these values move by local neighbor reads and texture ping-pong. Path length and region shape therefore determine update latency in the simulated substrate. That is a strong spatial property. It is not a resistance, capacitance, electromigration, crosstalk, or foundry-rule result.
The nested-instantiation wrapper explains how local configuration data and ownership use these neighboring relationships without modifying the preserved shader artifact.
Why Keep The Word “Metal”
The word is useful because it resists an easy abstraction error. A value does not teleport from one component to another. It occupies a path, crosses a boundary, consumes local connection capacity, and arrives after propagation.
The word becomes misleading only when logical adjacency is presented as physical closure. A future Cartilage implementation must map logical side-metals onto concrete FPGA routing or IC layers, extract or estimate delay, satisfy design rules, and close timing. The current public evidence has not crossed that boundary.
Wires Make Ownership Concrete
A nested component is not merely a name in a source file. Its boundary has ports; its ports occupy routes; its parent must reach them; and an independently reconfigurable child needs a configuration surface distinct from ordinary circuit composition.
The next chapter uses that physical intuition to distinguish nested source definitions, ordinary composed circuitry, and a genuinely owned daughter region.