An R&D Partner for Problems That Cross Hardware, Software, and Physics

FPGA and reconfigurable computing are one searchable doorway into a much larger practice. I work where hardware, software, signals, GPU and ML computation, distributed systems, and physical process meet—and where the inherited stack hides the decisive mechanism.

I am Brian Greenforest, a principal hardware and software engineer in Washington State. I follow hard systems from physical signals and device constraints through embedded code, RTL, services, data, interfaces, and operating products, then turn the boundary that matters into working evidence another team can inspect and extend.

The perfect fit is not a technology label. It is a problem that has fallen between disciplines and needs one person to preserve the whole mechanism while moving from architecture to implementation, diagnosis, prototype, measurement, or handoff.

Bring the hard cross-layer boundary Inspect public mechanisms Open résumé

The Search Term Is a Door, Not the Definition

Someone may arrive here by searching for an FPGA R&D partner, SystemVerilog verification, or reconfigurable-computing research. That tells me where the immediate pain sits. It does not define the limit of the work.

A real system may begin at an RF threshold, cross an FPGA, DMA path, embedded Linux service, network protocol, distributed control plane, database, and operator interface before the failure or opportunity becomes visible. Another problem may begin as a mathematical rule, become a shader or RTL machine, and end at timing, packaging, materials, or fabrication access. Treating those as unrelated specialties can hide the actual cause.

My contribution is continuity across those boundaries. I can reason from the physical mechanism upward and from the product behavior downward until both descriptions meet in something runnable, testable, and useful.

One Practice, Many Technical Forms

Mission-critical systems
Recent work spans Rust actor services, gRPC, ARM Linux, SCPI/IP instruments, Docker/systemd, and React control surfaces for more than 100 Amazon Leo electrical ground-support racks. The same cross-layer diagnosis has restored interrupted satellite hardware tests when faults crossed services, networks, power controls, CAN gateways, instruments, and UI state. See the public résumé.
Embedded, RF, and protocols
Embedded Linux, kernel and BSP paths, DMA, SDR, DQPSK, FPGA interfaces, direct RMII/ARP/UDP logic, adjacent-device configuration, and host-to-microcontroller control. The FPGA systems map exposes the public pin-to-bitstream evidence.
Products and distributed state
Full-stack recovery and architecture across React, C++, Node.js, Python, SQL, AWS, search indexes, media stores, synchronization, caching, offline recovery, marketplace workflows, and collaborative editing. The work includes ASU media/search recovery, Zoom chat state, Nintendo ordering, and conflict-aware multi-user products.
GPU, graphics, and simulation
Raw WebGL and GLSL computation, packed texture state, framebuffer passes, ping-pong simulation, cellular automata, procedural signed-distance rendering, and the path from graphics machinery toward general and AI compute architecture.
AI, ML, vision, and retrieval
Computer-vision architecture across local matching and global retrieval, Transformer inference and memory tradeoffs, embeddings and RAG, and a public four-layer Transformer training run with its command, loss trail, and generated samples preserved.
Novel computation
The streaming bit-serial multiplier, MUX algebra, Cartilage, local ownership and reconfiguration, physical logic tiles, and attempts to rebuild computation from switching, state, routing, timing, and composition rather than accept a fixed machine model.
Devices and fabrication
Maker-scale active-device research, wafer-diced chiplet substrates, magnetics, gain, restoration, fanout, interconnect, and physical-computing education. Here the work begins with materials and process boundaries instead of pretending the semiconductor toolchain is universally accessible.

These are not seven unrelated careers. They are places where the same method operates: identify the abstraction that is hiding the real behavior, reconstruct the missing mechanism, and make the result concrete enough to change the next engineering decision.

Cartilage as One Complete Evidence Chain

Cartilage Core is one substantial example of this practice, not the professional category. It starts with a spatial computing argument, makes local role, routing, ownership, and configuration visible in WebGL, states the hardware contract independently in SystemVerilog, checks it with Verilator, and carries a physical tile through an FPGA implementation flow.

The browser model installs 36 seven-bit records into a child-owned 6x6 region: 252 payload bits followed by one apply pulse. The independent RTL has no fabric-wide application clock; application and overlay signals remain continuous local levels while configuration state changes on routed local edges.

Current public revision48ff6e0, July 2026.

Working chain: WebGL reference behavior, canonical SystemVerilog checks, exact serial installation, differential checks for the flattened iCE40 encoding, and a recorded Yosys/nextpnr/icepack result for a fully edge-bonded 9x8 tile on iCE40HX8K-CT256.

Physical result: 72 cells, 5,513 LUT4, 1,512 DFF, 6,811 of 7,680 packed logic cells, and 205 of 206 bonded user I/O under that APP/C/D perimeter-interface and package-pin contract.

Boundary: architecture and FPGA implementation evidence, not board execution, timing closure, measured frequency or power, fabricated silicon, or a general compiler and placer/router.

Inspect current source Read routed result

The value is the movement across representations without confusing them: an argument is not a model, a model is not RTL, an RTL check is not a routed device, and a routed device is not a measured board. A difficult R&D program often needs exactly that continuity.

From Operating Systems to Open Research

Operating and recovered systems: satellite test infrastructure, railroad SDRs, embedded aerospace control, large media/search recovery, cross-platform communication state, and transaction-heavy products. This is engineering under real interfaces, failure modes, users, and delivery constraints.

Public mechanisms: one-pin RF receive and transmit paths, direct Ethernet and FPGA configuration, raw browser-GPU machines, streaming arithmetic, Cartilage, physical MUX tiles, and bounded ML artifacts. These make the method inspectable outside an employer or client context.

Open research: active-device fabrication, magnetic circuits, spatially reconfigurable substrates, wafer-diced self-assembling chiplets, visible-gradient learning machinery, and other questions that need laboratories, institutional support, or funded collaboration to become stronger machines.

What I Can Produce for a Team

System architecture
A coherent contract across devices, software, services, data, tests, deployment, operators, and the physical environment.
Failure recovery
Cross-layer diagnosis that follows a stalled run, missing packet, stale state, or broken workflow until the responsible boundary is isolated and repairable.
Executable model
A shader, simulator, software reference, mathematical construction, or other runnable form that makes the proposed mechanism visible.
Implementation
Embedded software, services, UI, RTL, GPU code, protocol logic, toolchain work, or a focused prototype designed around the actual boundary.
Verification and measurement
Self-checking tests, differential comparisons, exact vectors, traces, resource and timing reports, experiments, and a precise statement of what remains open.
Technical handoff
Source, reproduction paths, diagrams, design arguments, evidence notes, and a structure that lets the next engineer continue rather than start over.

Where I Fit a Funded Program or Product Team

The National Science Foundation uses categories such as Computer Systems Research and Software and Hardware Foundations. Its technology topics include computational architecture, processor design, AI, advanced manufacturing, and instrumentation and hardware systems. NIST describes CHIPS research and development as work to invent, develop, prototype, and deploy foundational semiconductor technologies.

I can contribute inside those programs, but the fit is broader than grant vocabulary. A product organization may need a principal engineer who can recover a system that crosses hardware and software. A research group may need an architecture turned into a reproducible artifact. A prime contractor may need a small-business technical partner. A laboratory may need someone who can connect an experimental mechanism to software, controls, data, and a credible next measurement.

I can join as a principal hardware/software engineer, independent R&D partner, systems architect, small-business subcontractor through Solid State Pros LLC, implementation collaborator, or technical lead for a bounded work package.

Bring the Boundary the Existing Stack Cannot Express

Email brian@solidstatepros.com with the system, the hard boundary, and what must change. It can be a source tree, architecture, instrument path, failing test, data flow, board interface, model, process hypothesis, or product workflow.

The useful first question is not whether it fits one specialty label. It is whether the decisive mechanism can be exposed and carried far enough to make the next decision possible.

Discuss the hard boundary See ways to work together Review professional experience