An R&D Partner for Problems That Cross Hardware, Software, and Physics

When a problem crosses hardware, software, signals, data, and physics, Brian Greenforest carries the whole mechanism from diagnosis into a working system.

Brian is a principal hardware and software engineer in Washington State whose work spans embedded systems, RTL, RF, GPU and ML computation, distributed services, interfaces, products, and semiconductor research.

The strongest fit starts with a consequential problem that has fallen between disciplines and needs one architect to preserve continuity from physical behavior through implementation, measurement, product operation, and handoff.

Bring the cross-layer problem Explore working systems Open résumé

The Search Term Opens The Door

An FPGA, SystemVerilog, or reconfigurable-computing search often names the layer where immediate pain appears. The complete solution may cross far more of the system.

An RF threshold may feed an FPGA, DMA path, embedded Linux service, network protocol, distributed control plane, database, and operator interface before the opportunity becomes visible. A mathematical rule may become a shader or RTL machine and then meet timing, packaging, materials, or fabrication access.

Cross-layer continuity finds the cause that isolated specialties can miss. Reasoning upward from physical behavior and downward from product behavior brings both descriptions together in a system that runs, measures, and creates value.

One Practice, Many Technical Forms

Mission-critical systems
Rust actor services, gRPC, ARM Linux, SCPI/IP instruments, Docker/systemd, and React control surfaces operate across more than 100 Amazon Leo electrical ground-support racks. Cross-layer diagnosis restores satellite hardware tests when faults cross services, networks, power controls, CAN gateways, instruments, and UI state. See the professional record.
Embedded, RF, and protocols
Embedded Linux, kernel and BSP paths, DMA, SDR, DQPSK, FPGA interfaces, direct RMII/ARP/UDP logic, adjacent-device configuration, and host-to-microcontroller control. The FPGA systems map follows those systems from physical pins through configured machines.
Products and distributed state
Full-stack recovery and architecture across React, C++, Node.js, Python, SQL, AWS, search indexes, media stores, synchronization, caching, offline recovery, marketplace workflows, and collaborative editing. The work includes ASU media/search recovery, Zoom chat state, Nintendo ordering, and conflict-aware multi-user products.
GPU, graphics, and simulation
Raw WebGL and GLSL computation, packed texture state, framebuffer passes, ping-pong simulation, cellular automata, procedural signed-distance rendering, and the path from graphics machinery toward general and AI compute architecture.
AI, ML, vision, and retrieval
Computer-vision architecture across local matching and global retrieval, Transformer inference and memory tradeoffs, embeddings and RAG, plus a four-layer Transformer trained on a CPU with its command, loss trail, and generated samples.
Novel computation
The streaming bit-serial multiplier, MUX algebra, Cartilage, local ownership and reconfiguration, and physical logic tiles rebuild computation from switching, state, routing, timing, and composition.
Devices and fabrication
Civic-scale active-device research, wafer-diced chiplet substrates, magnetics, gain, restoration, fanout, interconnect, and physical-computing education carry computation into materials and fabrication process.

One method connects these technical forms: find the abstraction that hides real behavior, reconstruct the decisive mechanism, and turn it into a system that changes the next engineering decision.

Cartilage Carries One Idea From Browser To FPGA

Cartilage Core begins with a spatial-computing architecture, makes local roles, routing, ownership, and configuration visible in WebGL, expresses the hardware contract independently in SystemVerilog, checks it with Verilator, and carries a physical tile through an FPGA implementation flow.

The browser installs 36 seven-bit records into a child-owned 6x6 region: 252 payload bits followed by one apply pulse. The independent RTL uses no fabric-wide application clock; application and overlay signals remain continuous local levels while routed local edges change configuration state.

July 2026 revision 48ff6e0 joins WebGL behavior, canonical SystemVerilog checks, exact serial installation, differential checks for flattened iCE40 encoding, and a Yosys/nextpnr/icepack result for a fully edge-bonded 9x8 tile on iCE40HX8K-CT256.

The routed result contains 72 cells, 5,513 LUT4, 1,512 DFF, 6,811 of 7,680 packed logic cells, and 205 of 206 bonded user I/O under the APP/C/D perimeter interface and package-pin contract.

Run the current source Read the routed result

The chain preserves meaning as the idea crosses argument, model, RTL, differential check, and routed device. Difficult R&D programs need that continuity to move confidently into board execution, timing, characterization, and product integration.

Operating Products And Original Research Reinforce Each Other

Operating systems: satellite test infrastructure, railroad SDRs, embedded aerospace control, large media/search recovery, cross-platform communication state, and transaction-heavy products exercise the work against real interfaces, users, and delivery constraints.

Public systems: one-pin RF receive and transmit paths, direct Ethernet FPGA configuration, raw browser-GPU machines, streaming arithmetic, Cartilage, physical MUX tiles, and a complete Transformer run expose the same cross-layer method for direct inspection and reuse.

Research programs: active-device fabrication, magnetic circuits, spatially reconfigurable substrates, wafer-diced self-assembling chiplets, and visible-gradient learning machinery create opportunities for laboratories, institutional partners, and funded collaboration.

What A Team Can Commission

System architecture
A coherent contract across devices, software, services, data, tests, deployment, operators, and the physical environment.
Failure recovery
Cross-layer diagnosis that follows a stalled run, missing packet, stale state, or broken workflow until it isolates and repairs the responsible mechanism.
Executable model
A shader, simulator, software reference, or mathematical construction that makes the proposed mechanism visible and usable.
Implementation
Embedded software, services, UI, RTL, GPU code, protocol logic, toolchain work, or a focused product slice built around the decisive mechanism.
Verification and measurement
Self-checking tests, differential comparisons, exact vectors, traces, resource and timing reports, and physical measurements that direct the next engineering decision.
Technical handoff
Source, reproduction paths, diagrams, design arguments, measurements, and a structure that lets the next engineer continue with full context.

Bring This Range Into A Funded Program Or Product Team

The National Science Foundation uses categories such as Computer Systems Research and Software and Hardware Foundations. Its technology topics include computational architecture, processor design, AI, advanced manufacturing, and instrumentation and hardware systems. NIST describes CHIPS research and development as work to invent, develop, prototype, and deploy foundational semiconductor technologies.

The fit extends beyond grant vocabulary. A product organization may need a principal engineer to recover a system that crosses hardware and software. A research group may need an architecture turned into an executable implementation. A prime contractor may need a small-business technical partner. A laboratory may need one engineer to connect a physical mechanism with software, controls, data, and the next decisive measurement.

Engagement can take the form of principal hardware/software engineering, independent R&D partnership, systems architecture, small-business subcontracting through Solid State Pros LLC, implementation collaboration, or technical leadership for a focused work package.

Bring The Problem The Existing Stack Hides

Email brian@solidstatepros.com with the system and the result that must change. Start from a source tree, architecture, instrument path, failing test, data flow, board interface, mathematical model, process hypothesis, or product workflow.

The first conversation finds the decisive mechanism and defines the shortest useful path toward an operating result.

Discuss the system See ways to work together Review professional experience