Brian Greenforest Builds Across The Whole Machine

Brian Greenforest smiling in a forest while holding a large yellow maple leaf
Brian Greenforest

Brian Greenforest turns hidden computational boundaries into working circuits, signal paths, spatial fabrics, browser-GPU machines, and product architectures.

Principal Hardware & Software Engineer · Remote · Washington State

Soviet aerospace education, decades of software engineering, Verilog and assembler, FPGA signal and protocol paths, browser-GPU systems, and hands-on physical design all converge on one practice: find where timing, state, routing, gain, or material behavior actually lives, then build the mechanism at that level.

Greenforest I/O names that engineering and invention practice and connects it to product development through Solid State Pros LLC.

One Builder, Complete Causal Paths

Most technical organizations divide a machine at the same abstraction boundaries every time. Brian crosses those boundaries when the product demands it: from an RF threshold at a pin through logic and recovered audio, from an Ethernet frame through packet state and adjacent-device configuration, or from a browser texture through a new model of spatial computation.

The bubbles-free bit-serial multiplier exposes arithmetic scheduling clock by clock. The FPGA systems connect thresholded RF, quadrature logic, RMII Ethernet, packet state, RAM, and configuration pins. The WebGL and GLSL machines use textures and framebuffer passes as direct computing state. The Cartilage architecture joins LUTs, drivers, distribution, state, timing, metal, composition, ownership, and runtime spatial replacement.

From Invention To An Engagement

Solid State Pros LLC carries the work into funded R&D, research architecture, product development, technical due diligence, and engineering roles.

Start directly: brian@solidstatepros.com.

The Primitive Pieces Connect Everything

Local ownership, switching, routing, restoration, gain, fanout, state, configuration, and repeatable process form a common alphabet. Rebuilding systems from that alphabet reveals architectures that a fixed software or hardware stack cannot express.

Serial arithmetic, one-pin radio, direct Ethernet and ARP logic, cross-device FPGA reconfiguration, physical MUX tiles, browser-GPU cellular automata, Cartilage reconfiguration, Transformer training, wafer-diced chiplets, and magnetic circuits all grow from that move.

The 210-problem map organizes the commercial reach into capability-native agency, live reconfigurable physical computation, and minimal-apparatus physical intelligence.

Public Mechanisms Create Momentum

Circuits, source, measurements, images, training runs, articles, and historical records give engineers multiple ways to enter the work. A reader can trace a clock, run a shader, inspect an RTL path, assemble a logic tile, or develop the next architecture.

The strongest next step joins these mechanisms with funding, customers, collaborators, laboratory and fabrication access, or an institution ready to turn the research into widely useful systems.