One-pin Weaver radio · physical I/Q combination
My transmitter is four quadrature mixers followed by a phase-domain summator. Two baseband I/Q sigma-delta streams undergo the first Weaver conversion. The resulting two one-bit signals control a four-state selector that realizes the two 216 MHz carrier mixers and their sum on one RF pin. N16 then excites a hand-built resonant tank.
At the wanted frequency, the I and Q products reinforce. At the conjugate frequency, they oppose. On July 26 the complete tank-to-receiver path placed a 223.5625 MHz wanted lane 29.44 dB above its 208.4375 MHz true conjugate image. A wider 500 kHz upper-sideband run produced the rectangular spectrum I wanted, with only 1.14 dB of level spread across its flat core.
A Weaver transmitter uses two quadrature mixer pairs: four mixers altogether. Physical27 sigma-delta encodes I and −Q into one bit each. A +7.5 MHz quadrant sequence performs the first mixer pair as exact swaps and inversions of the complete two-bit word. Its outputs are two one-bit intermediate signals.
Those two signals control a four-state selector. Each state is the algebraic result of the second pair of quadrature mixers operating on 0°, 90°, 180°, and 270° phases of the physical 216 MHz PLL clock. The selector is therefore a phase-domain summator: it realizes both 216 MHz carrier mixers and their sum on one RF pin. N16 switches that result high or high impedance into the tank.
Let Q′ denote the selected quadrature polarity; Physical27 uses Q′ = −Q. The first two mixer products form I1 = I·cos(IF) − Q′·sin(IF) and Q1 = I·sin(IF) + Q′·cos(IF). The second two mixer products enter the summator as I1·cos(LO) − Q1·sin(LO). The LO+IF terms reinforce while the LO−IF terms cancel. Reversing Q′ swaps which side survives.
The April 2025 mod_apr20.sv used opposing sawtooth baseband sources, two one-bit sigma-delta streams, the same four-mixer Weaver structure, and the same phase-domain summator. Physical27 is its architectural descendant: the frontend now generates PRBS16 QPSK, but the two one-bit intermediate signals, four physical carrier phases, high/high-impedance N16 boundary, and resonant tank remain.
On July 25 I sent a narrow QPSK upper branch through the FPGA, N16, tank, nominal 3 dB pad, and RTL-SDR. A deliberate +I pilot made the translated center conspicuous. Removing only that pilot pushed the center line down by 23.41 dB while changing wanted power by 0.01 dB and the local opposite branch by 0.08 dB.
With the pilot gone, the wanted branch stood 18.87 dB above the opposite branch and the residual translated center was 28.00 dB below the wanted signal. Visually, this was the orthogonal-looking spectrum I had been chasing: information occupied one side while the local opposite branch and translated center fell away.
Physical37 streamed signed 16-bit I and Q at 750 ksample/s into the FPGA SDM/DDS/Weaver path. The tank-coupled output filled a 500 kHz upper-sideband core from 223.25 to 223.75 MHz. Its P10-to-P90 level spread was 1.14 dB: visually and numerically close to the flat rectangular band I had been chasing.
I then retuned the same receiver to the true 208.2–208.8 MHz conjugate-image region and to the 216 MHz four-phase carrier. Across those sequential views, raw integrated wanted/image separation was 20.28 dB. The raw 216 MHz carrier was 5.70 dB below the wanted band; a coarse receiver-shape adjustment changed those ratios to 21.48 and 9.81 dB.
The three receiver views at the top use the v15 payload and path while the RTL-SDR tunes sequentially to the wanted band, true image, and carrier. Each view includes its own RF-off baseline. The uninterrupted run then continued after midnight. A later same-configuration four-view sweep improved the 500 kHz flat-core spread to 0.929 dB, placed the 216 MHz carrier 28.85 dB below the desired band, integrated a ±2 kHz translated-center window 38.39 dB below it while excluding the exact tuner-DC bin, and measured 22.52 dB desired/image separation.
Physical27 sent a narrow FPGA-native QPSK lane at 223.5625 MHz. Physical28 kept the FPGA image, gain, sample rate, cable path, and three-second gate unchanged, then moved only the RTL-SDR tuning to the predicted 208.4375 MHz conjugate image. Signed TX-on-minus-RF-off power in fixed 25 kHz windows gave a 29.44 dB wanted/image ratio.
Across five broad NanoVNA sweeps, S21 was about 7.95 dB higher at 223.5625 MHz than at 208.4375 MHz, so the tank clearly favored the wanted frequency. The NanoVNA sweep and sequential SDR captures used different instruments and reference planes; subtracting 7.95 dB from 29.44 dB would not isolate a digital-only Weaver cancellation figure.
The pMOS output does not synthesize a smooth voltage. It injects timed charge into the coupled resonant network and then releases the pin. Electric and magnetic energy continue exchanging in the tank between FPGA edges. That is why this transmitter is not merely a digital pin followed by cosmetic filtering: the RF waveform exists through the interaction of the phase sequence and the tuned matter.
My historical bench sketch notes about −15 dBm beside the earlier 7.5 kΩ coupling path. As a power unit, −15 dBm is 31.6 µW; if that power is delivered into 50 Ω, it corresponds to 39.8 mV RMS or about 112 mV peak-to-peak for a sine wave. The sketch does not name its load, output reference plane, bandwidth, cable correction, or instrument settings, so it remains the earlier noted tank value—not a July 2026 output-power measurement.
For the July 26 Physical27 run, the fixed 25 kHz wanted window integrated to −20.85 dB on the receiver analysis scale, and its peak reached −38.55 dBFS per FFT bin. The RTL-SDR chain had no injected reference supplying a frequency-and-gain calibration constant, so converting either number to dBm would invent a reference that was never measured. The next absolute-power pass must sample voltage at a named 50 Ω output plane with the exact bitstream, tank load, carrier setting, probe factor, scope termination, and path loss recorded together.
The hard part was not merely loading another bitstream. FPGA source, timing closure, volatile programming, live logic state, passive transfer, receiver tuning, RF-off baselines, packet recovery, and the next design decision all had to refer to the same physical event.
I set the architecture, the physical connections, the 222–225 MHz boundary, and the safety rules. The orchestration could then synthesize and place a one-variable change, reject a timing failure, arm telemetry and the RTL-SDR before programming, load only volatile CRAM, verify CDONE, capture one bounded burst, recover the received consequence, and return N16 to high impedance. In response-driven branches it selected the next discriminator from the previous physical result. Predetermined sweeps and unchanged repeats remained ordinary instrument mechanics.
Those counts span different instrument and programming operations across two calendar dates; they are not 258 interchangeable experiments. Receiver captures include RF-off guard time. Most FPGA images emitted one finite burst and then became electrically quiet at N16.
I began by untangling the fixture. The NanoVNA measured the passive network while the transmitter was off. The RTL-SDR then measured the active path with the NanoVNA powered down. Early captures checked tuner behavior, receiver gain, the idle state, finite on/off timing, harmonics within the receiver’s usable range, and whether the ADC hit its rails.
Five complex tank sweeps put the median S21 maximum at 220.783 MHz. The half-power crossings were 217.439 and 223.719 MHz, giving a 6.28 MHz loaded bandwidth and loaded Q of about 35.2. The later 223.5625 MHz QPSK lane lies about 156 kHz inside the upper half-power crossing. Its interpolated median S21 is about −23.22 dB, roughly 2.75 dB below the tank peak.
Then I asked the one-pin boundary a cleaner causal question: if only the sign of Q changes, does the physical RF component cross the carrier? It did. The received peak moved from about −997.9 Hz to +997.9 Hz around the measured midpoint, a 1.996 kHz separation. The same digital-to-physical boundary was controlling direction, not merely gating a carrier.
On July 26 I separated three physical questions that had been conflated: the wanted-band shape, the residual 216 MHz carrier, and the 208 MHz conjugate image. Each receiver tuning changed one observable boundary, so the next FPGA change could address one mechanism at a time.
The final Physical27 image did not stream payload samples from the host. A PRBS16 generator inside the FPGA began from 0x1D2B, advanced with the recurrence p15 ^ p13 ^ p12 ^ p10, and mapped lane 62 as {p5 ^ 1, p7}. Its four states were 0=+I, 1=+Q, 2=−I, and 3=−Q.
The timing-closed HX8K image used 2,127 of 7,680 logic cells, one of two PLLs, no block RAM, three global buffers, and seven I/O cells. The 12, 30, 108, and 216.03 MHz domains all passed their declared timing constraints. A 324,000,000-cycle gate created one nominal three-second burst at 3,295.9 symbols/s and 6,591.8 gross bits/s.
The April 2025 mod_apr20.sv transmitter used opposing sawtooth baseband sources, two sigma-delta streams, a quadrature IF mixer pair, and the same phase-domain summator for the second two mixers and their RF sum. V10 retains that four-mixer structure, the two one-bit intermediate signals, pMOS-only N16 boundary, and external tank. It replaces the baseband and IF implementation with FPGA-native PRBS QPSK, a complex lane waveform, signed SDMs, complete-word +7.5 MHz rotation, one-shot gating, and direct telemetry. It is a descendant, not a byte-equivalent rebuild of the April 2025 source.
Follow every v10 stage from PRBS state to N16, including source excerpts, constraints, the exact build command, and the source bundle used by the measured image.
Physical27 armed the RTL-SDR and direct telemetry before programming the FPGA. The receiver captured unsigned 8-bit complex samples at 2.4 MS/s, centered at 223.4875 MHz. The analysis mixed the 223.5625 MHz lane to baseband, averaged groups of 45 input samples, and applied a 257-tap 10 kHz low-pass filter. Channel energy located one 3.008-second burst without using the transmitted sequence.
A fourth-power carrier tracker learned its smoothing width from early directly observed epochs, then followed received I/Q during held-out data without using held-out truth or decisions. Timing, orientation, clock scale, complex gain, and offset were frozen from the early region. Each symbol came from 13 interpolated samples across the central 72% of its epoch.
The nominal held-out span contained 5,623 epochs. Direct telemetry reached 4,296 of them; 1,327 holes inside that span stayed absent. Across the entire run, 2,332 epochs were missing. None were reconstructed or scored. The 4,296 directly observed symbols became 8,592 checked bits with no observed errors, 2.07% carrier-tracked RMS EVM, and 0.9996 normalized correlation.
I ran the bench inside an RF chamber as a transmission-safety boundary. Each final profile used volatile configuration, N16 defaulted to high impedance, PLL or reset loss vetoed RF, and the board’s TX LED followed the real physical gate. Physical27 and Physical28 both ended with idle postflight telemetry: N16 high-impedance, burst inactive, and the TX LED off.
The chamber confined the bounded bursts, but no calibrated exterior field-strength sweep measured what escaped it. Distance, antenna factor, orientation, detector, bandwidth, ambient baseline, uncertainty, and field units were not part of the run, so chamber leakage and regulatory margin remain unquantified. The transmitter was not operated as an outdoor legal-power test.
Before the final FPGA-native PRBS experiment, a July 25 run used complex FM to pass a privacy-neutral spoken progress report through N16, the tank, the nominal 3 dB pad, and the RTL-SDR. The physical demodulation below lasts 9.79 seconds. Against its exact source-phase model, the longer fitted interval reached 0.869 correlation and 4.91 dB single-fit SNR, with a 56.8% EVM-like residual.
The audio is recognizably information-bearing and audibly imperfect. It belongs to the earlier FM branch, not the Physical27 QPSK payload.
The next work is traceable conducted power, common-clock timing, repeatability, and a wider experiment envelope.
Run bash scripts/build-v10.sh to regenerate the v10 netlist, route report, and FPGA image; all four declared clocks pass timing. The bundle includes the RTL, generated constants, constraints, build script, route summary, and scorer.
The source is available for study and reproduction; no separate reuse license has been granted.
RTL, generated tables, constraints, build script, route summary, and a local scoring program.
Open the build READMEThe privacy-clean held-out table and scorer recompute symbol errors, bit errors, RMS EVM, and normalized correlation.
Download 4,296 pointsOne ZIP contains the RTL, generated constants, constraints, build and scoring programs, route summary, and held-out points.
Download the v10 source bundle