One-pin Weaver radio · physical I/Q combination
Four quadrature mixers and a phase-domain summator turn two baseband I/Q sigma-delta streams into QPSK on one FPGA output pin. N16 switches among four phases of a 216 MHz PLL clock and excites a hand-built resonant tank.
At the wanted frequency, I and Q reinforce; at the conjugate image, they oppose. On July 26, the complete tank-to-receiver path placed a 223.5625 MHz lane 29.44 dB above its 208.4375 MHz image. A 500 kHz upper-sideband run filled a rectangular spectrum with 1.14 dB of level spread across its flat core.
A Weaver transmitter uses two quadrature mixer pairs. Physical27 sigma-delta encodes I and −Q into one bit each. A +7.5 MHz quadrant sequence performs the first pair through exact swaps and inversions of that two-bit word, producing two one-bit intermediate signals.
Those signals control a selector with four outputs: 0°, 90°, 180°, and 270° phases of the physical 216 MHz PLL clock. Each state already contains the algebraic result of the second mixer pair and their sum. N16 switches the selected phase high or high impedance into the tank.
Let Q′ denote the selected quadrature polarity; Physical27 uses Q′ = −Q. The first pair forms I1 = I·cos(IF) − Q′·sin(IF) and Q1 = I·sin(IF) + Q′·cos(IF). The summator then emits I1·cos(LO) − Q1·sin(LO). LO+IF terms reinforce while LO−IF terms cancel. Reversing Q′ selects the opposite sideband.
The April 2025 mod_apr20.sv used opposing sawtooth baseband sources, two one-bit sigma-delta streams, the same four-mixer Weaver structure, and the same phase-domain summator. Physical27 advances that architecture with FPGA-native PRBS16 QPSK while retaining two one-bit intermediates, four physical carrier phases, the high/high-impedance N16 boundary, and the resonant tank.
On July 25, a narrow QPSK upper branch crossed the FPGA, N16, tank, nominal 3 dB pad, and RTL-SDR. A deliberate +I pilot raised the translated center. Removing only that pilot dropped the center line by 23.41 dB while wanted power changed by 0.01 dB and the local opposite branch changed by 0.08 dB.
The pilot-free wanted branch stood 18.87 dB above the opposite branch and 28.00 dB above the translated center. Information occupied one side while both competing features fell away.
Physical37 streamed signed 16-bit I and Q at 750 ksample/s into the FPGA SDM/DDS/Weaver path. The tank-coupled output filled a 500 kHz upper-sideband core from 223.25 to 223.75 MHz with only 1.14 dB of P10-to-P90 level spread.
Sequential receiver tunings then captured the true 208.2–208.8 MHz conjugate image and the 216 MHz four-phase carrier. Raw integrated wanted/image separation reached 20.28 dB. The raw carrier sat 5.70 dB below the wanted band; coarse compensation for receiver shape placed the ratios at 21.48 and 9.81 dB.
The three views above share the v15 payload and signal path, with one RF-off baseline per tuning. After midnight, a same-configuration four-view sweep tightened the 500 kHz flat-core spread to 0.929 dB, placed the carrier 28.85 dB below the desired band, placed a ±2 kHz translated-center window 38.39 dB below it while excluding the tuner-DC bin, and measured 22.52 dB desired/image separation.
Physical27 sent an FPGA-native QPSK lane at 223.5625 MHz. Physical28 retained the FPGA image, gain, sample rate, cable path, and three-second gate, then moved only the RTL-SDR tuning to the predicted 208.4375 MHz conjugate image. Signed TX-on-minus-RF-off power in fixed 25 kHz windows produced a 29.44 dB wanted/image ratio.
Five broad NanoVNA sweeps measured S21 about 7.95 dB higher at 223.5625 MHz than at 208.4375 MHz, showing how the tank favored the wanted frequency. The NanoVNA and SDR used different instruments and reference planes: 7.95 dB describes tank transfer, while 29.44 dB describes the complete sequential transmitter-to-receiver path.
The pMOS output injects timed charge into the coupled resonant network, then releases the pin. Electric and magnetic energy continue exchanging in the tank between FPGA edges. The phase sequence and tuned matter create the RF waveform together.
A historical bench sketch records about −15 dBm beside the earlier 7.5 kΩ coupling path. As a power unit, −15 dBm equals 31.6 µW; into 50 Ω, that equals 39.8 mV RMS or about 112 mV peak-to-peak for a sine wave. The sketch records the tank value without a load, output plane, bandwidth, cable correction, or instrument setup, so it remains distinct from the July 2026 receiver-relative measurements.
For the July 26 Physical27 run, the fixed 25 kHz wanted window integrated to −20.85 dB on the receiver analysis scale, and its peak reached −38.55 dBFS per FFT bin. Those values preserve the RTL-SDR's receiver-relative reference. An absolute-power pass can sample voltage at a named 50 Ω output plane and record the exact bitstream, tank load, carrier setting, probe factor, scope termination, and path loss together.
FPGA source, timing closure, volatile programming, live logic state, passive transfer, receiver tuning, RF-off baselines, packet recovery, and the next design decision all referred to the same physical event.
The run fixed the architecture, physical connections, 222–225 MHz operating band, and safety rules. Orchestration could then synthesize one variable, reject a timing failure, arm telemetry and the RTL-SDR before programming, load volatile CRAM, verify CDONE, capture one bounded burst, recover its received consequence, and return N16 to high impedance. Response-driven branches chose the next discriminator from the preceding physical result; predetermined sweeps and unchanged repeats handled instrument mechanics.
Those counts span distinct instrument and programming operations across two calendar dates. Receiver captures include RF-off guard time. Most FPGA images emitted one finite burst and then returned N16 to electrical silence.
The NanoVNA measured the passive network with the transmitter off. The RTL-SDR then measured the active path with the NanoVNA powered down. Early captures established tuner behavior, receiver gain, idle state, bounded on/off timing, harmonics within the receiver's usable range, and ADC headroom.
Five complex tank sweeps put the median S21 maximum at 220.783 MHz. The half-power crossings were 217.439 and 223.719 MHz, giving a 6.28 MHz loaded bandwidth and loaded Q of about 35.2. The later 223.5625 MHz QPSK lane lies about 156 kHz inside the upper half-power crossing. Its interpolated median S21 is about −23.22 dB, roughly 2.75 dB below the tank peak.
Changing only the sign of Q asked a clean causal question: would the physical RF component cross the carrier? The received peak moved from about −997.9 Hz to +997.9 Hz around the measured midpoint, a 1.996 kHz separation. The digital-to-physical boundary controlled direction as well as carrier gating.
On July 26, three receiver tunings separated the wanted-band shape, residual 216 MHz carrier, and 208 MHz conjugate image. Each tuning exposed one observable, letting the next FPGA change address one mechanism.
A PRBS16 generator inside Physical27 began from 0x1D2B, advanced with p15 ^ p13 ^ p12 ^ p10, and mapped lane 62 as {p5 ^ 1, p7}. Its four states carried 0=+I, 1=+Q, 2=−I, and 3=−Q.
The timing-closed HX8K image used 2,127 of 7,680 logic cells, one of two PLLs, no block RAM, three global buffers, and seven I/O cells. The 12, 30, 108, and 216.03 MHz domains all passed their declared timing constraints. A 324,000,000-cycle gate created one nominal three-second burst at 3,295.9 symbols/s and 6,591.8 gross bits/s.
The April 2025 mod_apr20.sv transmitter used opposing sawtooth baseband sources, two sigma-delta streams, a quadrature IF mixer pair, and the same phase-domain summator. V10 retains four mixers, two one-bit intermediate signals, the pMOS-only N16 boundary, and the external tank. FPGA-native PRBS QPSK, a complex lane waveform, signed SDMs, complete-word +7.5 MHz rotation, one-shot gating, and direct telemetry replace the earlier baseband and IF implementation.
Follow every v10 stage from PRBS state to N16, including source excerpts, constraints, the exact build command, and the source bundle used by the measured image.
Physical27 armed the RTL-SDR and direct telemetry before programming the FPGA. The receiver captured unsigned 8-bit complex samples at 2.4 MS/s around 223.4875 MHz. Analysis mixed the 223.5625 MHz lane to baseband, averaged groups of 45 input samples, applied a 257-tap 10 kHz low-pass filter, and located one 3.008-second burst through channel energy alone.
A fourth-power carrier tracker learned its smoothing width from early directly observed epochs, then followed received I/Q during held-out data without consulting held-out truth or decisions. The early region fixed timing, orientation, clock scale, complex gain, and offset. Thirteen interpolated samples across the central 72% of each epoch produced every symbol.
The nominal held-out span contained 5,623 epochs. Direct telemetry reached 4,296; 1,327 holes remained absent. Across the complete run, 2,332 epochs lacked telemetry, and the scorer omitted them. The 4,296 observed symbols yielded 8,592 checked bits with zero errors in this burst, 2.07% carrier-tracked RMS EVM, and 0.9996 normalized correlation.
The bench operated inside an RF chamber. Every final profile used volatile configuration, defaulted N16 to high impedance, vetoed RF after PLL or reset loss, and drove the TX LED from the physical gate. Physical27 and Physical28 ended with N16 at high impedance, the burst inactive, and the TX LED off.
The chamber confined each transmission. A calibrated exterior field-strength sweep can add distance, antenna factor, orientation, detector, bandwidth, ambient baseline, uncertainty, and field units for regulatory work. These runs stayed inside the chamber and exercised system behavior rather than outdoor legal-power operation.
Before the FPGA-native PRBS run, a July 25 complex-FM image carried a privacy-neutral spoken report through N16, the tank, the nominal 3 dB pad, and the RTL-SDR. The physical demodulation lasts 9.79 seconds. Against its exact source-phase model, the longer fitted interval reached 0.869 correlation and 4.91 dB single-fit SNR, with a 56.8% EVM-like residual.
The recognizable audio records the earlier FM branch; Physical27 later replaced it with FPGA-native QPSK.
Traceable conducted power, common-clock timing, repeatability, and additional operating modes can turn the working loop into a broader RF development platform.
Run bash scripts/build-v10.sh to regenerate the v10 netlist, route report, and FPGA image. All four declared clocks pass timing. The bundle includes RTL, generated constants, constraints, the build script, route summary, scorer, and held-out points.
Brian publishes the source for study and reproduction and retains all reuse rights unless he grants a separate license.
RTL, generated tables, constraints, build script, route summary, and a local scoring program.
Open the build READMEThe privacy-clean held-out table and scorer recompute symbol errors, bit errors, RMS EVM, and normalized correlation.
Download 4,296 pointsOne ZIP contains the RTL, generated constants, constraints, build and scoring programs, route summary, and held-out points.
Download the v10 source bundle