One FPGA Pin Performs A Weaver RF Sum

FPGA Weaver radio · April 2025 RTL

Four quadrature mixers collapse into one phase-switched FPGA pin and a resonant network.

Transmitter sawtooth waveforms, hand-built resonant-tank hardware, and a historical RF spectrum display — Opposing I/Q sawtooths drive the four-mixer structure, one pin excites the hand-built resonant network, and the receiver displays the resulting signal near 245.388 MHz.

The first mixer pair produces rfI and rfQ. Together, those bits address a four-state selector. Each state equals one algebraic sum of the second 216 MHz quadrature mixer pair, so the selector performs both carrier mixing and phase-domain summation before one selected phase reaches N16 and the tank.

A July 2026 descendant replaces the baseband and IF implementation with PRBS QPSK and a +7.5 MHz whole-word rotation while preserving the four mixers, two one-bit intermediate signals, phase-domain summator, N16 output, and tank. The historical tank sketch labels a 7.5 kΩ coupling path and records “about −15 dBm” beside the output.

Four Mixers Become One Selectable Phase

The April 2025 transmitter is in one-pin-RF/ptc_nov21/mod_apr20.sv. The adjacent build script, HX8K constraints, and nextpnr timing declarations use the open Yosys, nextpnr, IceStorm, and iceprog path.

Opposing 32-bit sawtooths create complex baseband motion, and two sigma-delta paths reduce I and Q to one bit each. A Johnson counter supplies the quadrature IF oscillator; adjacent taps drive the first mixer pair. The complete quadrature relationship rejects the conjugate image, and the resulting rfI/rfQ pair controls the selector that performs the phase-domain sum.

The Phase-Domain Summator Realizes Two 216 MHz Mixers and Their Sum

The source names two PLL outputs pll_216mhz and pll_216mhz_90. Their complements supply the other two phases. The four selector states encode every possible algebraic result of the two quadrature carrier mixers:

wire p1 =  pll_216mhz;
wire p2 =  pll_216mhz_90;
wire p3 = ~pll_216mhz;
wire p4 = ~pll_216mhz_90;

assign MODULATED_RF_OUT = rfI ? (
  rfQ ? p1 : p4
) : (
  rfQ ? p2 : p3
);

Each rfI/rfQ combination chooses the carrier phase equal to the sum of those two mixer products. The selector is therefore a phase-domain summator: it realizes the second mixer pair and their sum without two analog RF outputs or a downstream summer.

Hand sketch of four phase-offset carrier waves and their square-wave equivalents — The four carrier phases and their square-wave equivalents reveal how each selector state chooses the algebraic sum of the two carrier products.

The First Mixer Pair Produces `rfI` and `rfQ`

Two sawtooth states move in opposite directions. Each feeds a one-bit sigma-delta path, producing dac_out and dac_outQ. Adjacent quadrature IF phases mix with those streams to produce the two one-bit intermediate signals.

sawtooth  <= sawtooth  - 32'd148000;
sawtoothQ <= sawtoothQ + 32'd148000;

wire rfI = dac_out  ^ j_0[0];
wire rfQ = dac_outQ ^ j_0[1];

The first two mixers create rfI and rfQ; those bits control the four-state selector that realizes the second two mixers and performs their phase-domain sum. Image rejection comes from that complete quadrature relationship: the wanted products reinforce while the conjugate products oppose.

N16 Becomes The Physical Summation Point

The HX8K CT256 constraint file maps RF_OUT to N16. Instead of an ordinary push-pull data assignment, an SB_IO primitive holds the data side high and applies MODULATED_RF_OUT to OUTPUT_ENABLE, using the pMOS side as the RF switch.

SB_IO #(
  .PIN_TYPE(6'b101000),
  .IO_STANDARD("SB_LVCMOS"),
  .PULLUP(1'b0)
) ddr_io_1 (
  .PACKAGE_PIN(RF_OUT),
  .D_OUT_0(1'b1),
  .OUTPUT_ENABLE(MODULATED_RF_OUT)
);

The FPGA chooses the phase at N16; the external network stores energy and turns those switched edges into narrowband electrical behavior.

The Resonant Tank Turns Edges Into RF

Hand sketch of an FPGA square-wave output feeding a coupled resonant-tank network — The output-network sketch sends the FPGA switch through a series resistor and coupling capacitor into a parallel resonant primary and coupled secondary. The handwritten output annotation reads about −15 dBm.

A phase-switched digital pin produces edges and harmonics. The tank stores field energy between those edges, favors the intended RF region, and couples a sinusoidal output from its secondary. The historical sketch shows a 7.5 kΩ coupling value; the July 2026 fixture uses a nominal 8.5 kΩ value and measures a loaded tank Q of about 35.2.

The Receiver Shows The Local Signal Beside Live Radio

Historical CubicSDR display from an RTL-SDR Blog V4 showing the local FPGA transmitter and a live PTC channel — An RTL-SDR Blog V4 receives the local one-pin FPGA transmitter through the 8.5 kΩ coupling resistor and resonant tank beside a live PTC channel in the same CubicSDR view.

The local signal carries the expected sawtooth-like spectral shape beside the live channel. The 2026 continuation adds RF-off subtraction, fixed receiver windows, measured tank transfer, and separate views of the wanted band, 216 MHz carrier, and 208 MHz true image.

Why This Transmitter Matters

The design compresses four quadrature mixers and their final sum into FPGA primitives and one physical output: two one-bit intermediate signals, four carrier phases, one phase-domain summator, one switched pin, and one resonant network.

It creates a direct route from digital modulation state to RF phase and removes the conventional external I/Q modulator between the FPGA and tuned output network. That opens compact transmitter paths whose signal architecture lives almost entirely in reprogrammable logic.