Static Elaboration Meets Dynamic Work

An FPGA build fixes resource use into a bitstream. When every LUT has a role, another line of hardware logic requires a new allocation and compile cycle. C and C++ offer malloc and new; JavaScript and Python let objects gain relationships at runtime.

Accelerator APIs still force programmers to manage kernels, buffers, and communication across artificial boundaries. That machinery obscures the application’s own object model.

Give Reconfigurable Hardware a Native Runtime

Cartilage treats regions and connections as allocatable resources. Objects can create contained objects, attach ports, move references, and reshape local logic without turning the whole machine into a centrally managed FPGA build.

Software-language designers and FPGA engineers can work together on this post-von-Neumann model. Bring dynamic semantics to the fabric and let hardware scale as one homogeneous program.

Locate Allocation in the FPGA Fabric

The architecture chapter shows where LUTs, registers, wires, and routes live; the parallel-language and multiplier links carry allocation into source semantics and arithmetic structure.

See where LUTs, registers, wires, and routed module connections live inside an FPGA · Who Is Solving Parallel Source Code? · Bit-Serial Bubbles-Free Multiplier