Original Post

Yes, but:
1. After all LUTs are occupied, I can't add a new line of Verilog. In C and C++ I can.
2. In C I can malloc(), in C++ I can new. In Verilog all I can do is to reserve a fixed-size array and waste a lot of resources.
3. In JavaScript and Python I can say "obj.newField = anotherObjRef" and then "obj.newField.anotherObjRef.method(arg)". In OpenCL, oneAPI, CUDA, etc. nonsense I have to use MPI to even pass function arguments between kernels.

No, FPGAs are NOT cool. In fact, they are just CHIPS, but programmatically defined (and redefined).

We (software developers!) demand a post-von Neumann architecture! Reactive programmers who love OOP got tired of the von Neumann bottleneck, and FPGAs in their pure globally managed state are not a solution, even in a Kubernetes cloud cluster with clever Linux drivers.

We need a new distributed massively parallel PROGRAMMING LANGUAGE that runs on a breakthrough new innovation, a cluster of organically and scalably managed FPGAs. That can scale by just adding more servers to it. Homogeneously.