Cartilage Project Structure, 2022
April 27, 2022

Cartilage turns a new computer architecture into an executable program of work. Four connected projects move from choosing the right fabric cell to manufacturing hardware, running self-reprogramming objects, and expressing applications in a distributed language.

Each layer answers a concrete question and feeds the next, creating a direct path from transistor-scale choices to human-readable software.

Four Projects Define the Build

The emulator measures candidate cells: D flip-flops, MUX networks, LUTs, and SerDes bandwidth for communication between nodes. Sinew provides the overlay control network that changes neighboring configurations.

Stock-FPGA hardware carries the model into physical devices. Earlier board designs used Lattice iCE40LP384-SG32 parts on cuttable flex circuits and iCE40HX1K-TQ144 parts on a modular four-layer board.

Cartilage and the Language Complete the Stack

The Cartilage runtime manages zones, ports, routes, contained-object creation, and dynamic types across the emulator, FPGA array, or custom silicon. One process can represent one reactive value or operation.

The language layer gives programmers a distributed, massively parallel surface for that machine. Emulator builders, FPGA engineers, runtime designers, and language creators can take ownership of one layer and connect it to the whole.

Open the Cartilage Core Behind Cartilage Project Structure, 2022

The public core and its repository carry this architecture into source-backed, executable reconfigurable computation.

Cartilage Visual Language · Cartilage Core · public source repository

Originally posted on LinkedIn

Brian Greenforest · (2022-04-27 19:22:44 UTC)

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The following are projects (in the order of laser-sharp short term focus) we are working on (volunteer's help appreciated; early co-founder opportunities for creation of an invention that will be called "XXI century's Manhattan Project"). 1. Emulation of arbitrary FPGA element size to pick the optimal number of D flip-flops, multiplexer networks, LUTs, and optimal SerDes bandwith for inter-node communication. An early prototype was written in GLSL and contained only 1 reconfigurable multiplexer as a unique hyper-fine-grained switching fabric. Turns out, we needed to control adjacent FPGA configurations in every node, and it need much more than one multiplexer, otherwise it's a waste of reconfiguration support circuits. No need to compute next state fast, because only physical chips can run the model fast and efficiently. The selection research is in works right now (I wish I had less ADHD), and it's a JavaScript Node.js app, emulating a small array of interconnected FPGAs controlled by special control plane overlay network we codename "Sinew". 2. Manufacturing of physical prototypes using stock FPGAs. We ran out of available chips. Were using flex PCB design that allows to cut compute fabric with scissors (iCE40LP384-SG32). Another was a high-bandwidth FIFO-rich iCE40HX1K-TQ144 (a nice scalable modular PCB design has been made; but these chips had disappeared as well). 3. Zones-managing virtual machine we codename "Cartilage". It runs on top of the emulator, or the stock FPGAs prototype, or the optimal element physical chip. It allows to implement reactive programming with automatic ports route management and contained objects instantiations, and dynamic types creation at run-time. 4. Distributed massively parallel programming language syntax. Didn't touch yet, but it seems in a close reach (perhaps this year, even!)

Try Cartilage: Run the open one-slot multiplier.

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