Learning Verilog changed Brian Greenforest’s idea of programming. Boolean functions and registers became a language for constructing live parallel machinery, far more than a lower-level implementation behind software.

That shift connected decades of work in multithreading, streaming, low latency, time series, and model updates to one central goal: push a changed region of a giant distributed machine in under a second.

Program the Machine’s Structure

Sequential software tells a processor which instruction to execute next. Verilog defines registers, combinational paths, interfaces, timing, and many operations that exist at once.

That structural program allocates registers, memories, arithmetic, and routes as part of the machine instead of requesting them later through malloc, new, or garbage collection. Setup and hold requirements, pipeline latency, FIFOs, buses, handshakes, SerDes lanes, clock-domain crossings, and explicit state ownership become program structure rather than hidden platform behavior.

Open tools such as Yosys showed that fast compilation could support a web developer’s iteration rhythm. The remaining architecture must make partial reconfiguration serve application-scale changes across many devices.

Cartilage Makes Reconfiguration the Programming Model

Cartilage treats configured regions, ports, and connections as runtime objects. That model can join FPGA parallelism with statecharts, reactive dataflow, dynamic allocation, and a coherent distributed program.

Software developers who want direct control of parallel hardware can start with Verilog, then follow the path toward Cartilage’s reconfigurable machine.

Carry Verilog From Module to Working FPGA

The FPGA lab builds and verifies a module, Cartilage Visual Language exposes its spatial structure, and the cellular-automata experiments extend it across a programmable lattice.

build a module, select a top, write a self-checking testbench, and bind board constraints · Cartilage Visual Language · cellular automata experiments

Originally posted on LinkedIn

Brian Greenforest · Monday, April 18, 2022 at 12:57:08 PM PDT (2022-04-18 19:57:08 UTC)

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In 2019, I learned the model of computation of Verilog. For almost three decades, I was writing application software and soldering digital circuits. I mean, I KNEW it was Boolean functions combined with registers. But what I didn't know that it was a PROGRAMMING language. Most of my career, I was obsessed with multithreading, multiprocessing, streaming, low-latency, time series, pattern matching, and model updating. This #multicore thing was always with us, since Alan Turing and John von Neumann gave us the CPU core. It was obvious we CAN and SHOULD link them together. What the giants (on shoulders of whom we all stand today!) didn't have time to think and to tell us is that the distributed program above all these CONNECTED CORES is ONE single program (of choice, indeed, multi-tenant architecture sharing the same supercomputer or data center is a STANDARD expectation). What happened in 2019 is that I LOST ABILITY to write sequential applications FOR FUN. I became obsessed with the NEED to PUSH updated piece of my Verilog code into a GIANT (scalable, remember, I'm a software developer--I love to write MILLIONS and use BILLIONS lines of code) #fpga with my web developer's expectation of HOW LONG it should take (under one second is the best, as YosysHQ has shown to be possible). Then, it turns out, nobody on Earth manufactures FPGAs with partial reconfiguration targeting my needs. I can't stop working on the Project Cartilage until it's done. I need my application developer's FUN back!