Original Post

Have you ever thought that you can write a mini-FPGA code and instantiate it in the rest of your Verilog code, and feed it with your custom mini bitstream? It's just a programming style! Nothing special, but very extraordinary in the end. You can run thousands of mini-FPGA instances inside of your bigger FPGA instead of thousands of RISC-V cores!

Stay in the Boolean logic land. Don't fall for instruction pointers, stacks, and registers earlier than you have to. Why abandon massively parallel reactive objected oriented perfect components style in favor of sprinkling with some C? I don't understand how we got here? Premature optimization for microprocessors and microcontrollers?

Not all problems require a Von Neumann CPU. Especially, NP-hard ones...

#asic #asicdesign #fpga #parallelprogramming #scripting #verilog