Mini-FPGAs Inside FPGAs
June 18, 2021

A larger FPGA can contain thousands of smaller programmable fabrics, each with its own compact bitstream. That programming style creates dynamic hardware regions without inserting a RISC-V processor wherever behavior may change.

Brian Greenforest’s mini-FPGA pattern keeps computation in the massively parallel Boolean domain until a true instruction stream adds value.

Instantiate Reconfiguration as a Component

A mini-FPGA module contains LUTs, registers, routing MUXes, configuration state, and application-facing ports. The surrounding Verilog can create many instances and feed each one a custom configuration.

Those regions behave like dynamically selectable components inside the larger circuit. They can host local control, dataflow, state machines, or specialized functions while preserving direct hardware relationships.

Choose Structure Before Software

Stacks, instruction pointers, and register files bring familiar software semantics, yet they also serialize work. A reconfigurable region can express the same changing behavior through parallel logic and local state.

Start with conventional FPGA architecture, inspect the Cartilage Core, and build a mini-fabric whose configuration matches the application instead of forcing the application through another CPU.

Locate the Mini-FPGA Inside the Fabric

The FPGA architecture chapter identifies LUTs, flip-flops, and routes; Cartilage Core carries those resources into a nested reconfigurable system.

start with the conventional FPGA architecture chapter · Cartilage Core · public source repository

Originally posted on LinkedIn

Brian Greenforest · (2021-06-18 02:07:35 UTC)

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Have you ever thought that you can write a mini-FPGA code and instantiate it in the rest of your Verilog code, and feed it with your custom mini bitstream? It's just a programming style! Nothing special, but very extraordinary in the end. You can run thousands of mini-FPGA instances inside of your bigger FPGA instead of thousands of RISC-V cores! Stay in the Boolean logic land. Don't fall for instruction pointers, stacks, and registers earlier than you have to. Why abandon massively parallel reactive objected oriented perfect components style in favor of sprinkling with some C? I don't understand how we got here? Premature optimization for microprocessors and microcontrollers? Not all problems require a Von Neumann CPU. Especially, NP-hard ones... #asic #asicdesign #fpga #parallelprogramming #scripting #verilog

Comments added by Brian Greenforest on LinkedIn

These 2 comments were also preserved verbatim from Brian Greenforest’s LinkedIn data export or the public post page.

"hardware IP that also runs as efficient host software via "software style" methodology" is the very thing I am so strongly advocating against. How can I explain and deliver the message?..

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After a deeper dive I'm even more puzzled than before. Why they so badly dislike Verilog? 😹

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