This is a visual placement sketch for a 4-bit conditional incrementer.

The intended circuit is OUT = ENABLE ? (IN + 1) : IN.

That is the small control block behind a program-counter step, sequencer advance, DMA address bump, or state machine register that either holds its value or moves to the next value.

Visual placement sketchThis page is part of the Cartilage Run and Sketch Index.

Included: a 55x55 visual placement sketch, a 3080x3080 PNG, the intended OUT = ENABLE ? (IN + 1) : IN function, and the local island decomposition.

Sketch focus: repeated bit-slice structure, carry propagation, edge route intent, and the mapping from incrementer equations into Cartilage cell roles.

The Rendered Artifact

Cartilage fabric render of a 4-bit conditional incrementer with IN lanes from the left, ENABLE from the top, OUT lanes to the right, and final carry C4 — A 55x55 Cartilage visual placement sketch of a 4-bit program-counter stepper. The full-resolution image is linked for reading the routes.

What This Page Shows

The render shows the intended placement vocabulary for a small control datapath: left-edge input routes, top-edge enable, repeated local bit slices, carry propagation, and right-edge output routes.

For checked arithmetic behavior, use the Cartilage Verified Ripple2 Adder. For the current mechanism and hardware reference, use Cartilage Core; use Cartilage 2026, the visual language, and the nested-instantiation demo for the browser-artifact lineage.

The Stepper Function

In the intended stepper, each bit slice receives one input bit and one carry bit. The carry seed is C[0] = ENABLE, so the circuit increments only when enable is asserted.

OUT[i]    = IN[i] xor C[i]
C[i + 1] = IN[i] and C[i]
C[0]     = ENABLE

When ENABLE is zero, the first carry is zero and every output bit copies its input. When ENABLE is one, the carry ripple performs the ordinary increment-by-one operation.

MUX Island Decomposition

The Cartilage placement uses mux-friendly local logic islands. Each bit slice is decomposed into a local inversion island, an output toggle island, and a carry island:

notIN[i] = IN[i] ? 0 : 1
OUT[i]   = C[i] ? notIN[i] : IN[i]
C[i + 1] = IN[i] ? C[i] : 0

The repeated structure is the point of the render. It is easier to inspect than a single adder because the four slices show the same local rule repeated with a visible carry chain.

How To Read The Routes

ENABLE enters from the top edge and seeds C0. IN0 through IN3 enter from the left edge. OUT0 through OUT3 leave to the right edge, and the final overflow carry C4 is also routed to the right edge.

The sea around the active logic is mostly constant-zero cells. It is intentionally spacious so the repeated slice structure, local toggle islands, carry islands, intersections, and edge routes stay readable.

Data I/O Is Ordinary Fabric Routing

In the sketch, the data inputs and outputs are ordinary metal adjacency through neighboring fabric cells. Reconfiguration-port cells are not used for these data paths.

That distinction is part of the Cartilage model: reconfiguration ports change fabric state, while this screenshot is meant to show a configured control/arithmetic datapath carrying runtime data through local wires, intersections, constants, and MUX behavior.

Render Notes

The rendered lattice is 55x55 cells. The PNG is 3080x3080 pixels. It is a cycle-zero initialized-cell schematic with 19 semantic labels.

The labels are callouts for the human reader, not extra tile roles. The cell vocabulary is the same Cartilage render alphabet decoded in the Cartilage Visual Language article.

Where It Fits

The useful part is the placement vocabulary. Cartilage Core and its public source repository are the current mechanism and hardware reference. They do not turn this older cycle-zero placement sketch into a driven or verified counter.