Cartilage PC Stepper Islands: A Spatial 4-Bit Incrementer

Four repeated MUX slices turn one enable signal into a spatial program-counter step: hold the current word or advance it by one.

The circuit implements OUT = ENABLE ? (IN + 1) : IN across a 55x55 Cartilage placement map with a visible carry route from bit zero through bit three.

The 3080x3080 image exposes the control block used by program counters, sequencers, DMA address generators, and state registers as nineteen labeled roles and routes.

Read The Four-Bit Stepper As One Spatial Circuit

A 55 by 55 Cartilage incrementer map with four left-edge inputs, top-edge ENABLE, four right-edge outputs, and final carry C4 — Four repeated bit slices carry ENABLE from C0 through C4 while IN0–IN3 enter from the left and OUT0–OUT3 leave at the right.

See Hold And Increment Share The Same Datapath

Left-edge inputs, a top-edge enable route, four local toggle islands, four carry islands, and right-edge outputs make OUT = ENABLE ? (IN + 1) : IN visible from end to end.

The Cartilage Verified Ripple2 Adder runs a related carry structure across every input pair. Cartilage Core supplies the current browser and hardware mechanism; Cartilage 2026, the visual language, and the nested-instantiation mechanism connect this map to the full architecture.

Seed The Carry Chain With ENABLE

Each bit slice consumes one input bit and one carry bit. C[0] = ENABLE makes the first carry the control input for the entire word.

OUT[i]    = IN[i] xor C[i]
C[i + 1] = IN[i] and C[i]
C[0]     = ENABLE

With ENABLE at zero, every output copies its input. With ENABLE at one, the carry ripples through each asserted input bit and performs the increment-by-one operation.

Decompose Each Bit Into Three MUX Islands

Each slice combines a local inversion island, an output-toggle island, and a carry island:

notIN[i] = IN[i] ? 0 : 1
OUT[i]   = C[i] ? notIN[i] : IN[i]
C[i + 1] = IN[i] ? C[i] : 0

MUX Algebra derives the selector form behind every inversion, output toggle, and carry decision.

Four visible repetitions reveal how one local rule scales across a word while the carry chain links each slice to its neighbor.

Trace Every Input, Carry, And Output

ENABLE enters from the top and seeds C0. IN0 through IN3 enter from the left. OUT0 through OUT3 and the overflow carry C4 leave at the right.

A spacious constant-zero sea separates the active logic so each toggle island, carry island, intersection, and edge route remains legible.

Route Runtime Data Through Neighboring Cells

Ordinary metal adjacency carries inputs, carries, and outputs through neighboring fabric cells. Reconfiguration ports retain the separate job of installing or replacing cell roles.

The mapped datapath carries runtime values through local wires, intersections, constants, and MUXes while the configuration plane remains structurally distinct.

Decode The 55x55 Fabric At Full Resolution

The lattice contains 55x55 cells, and the PNG spans 3080x3080 pixels. Cycle-zero initialized roles form the circuit beneath 19 semantic labels.

Human-readable callouts name the signals, while the Cartilage Visual Language decodes the installed cell roles beneath them.

Carry The Placement Pattern Into A Running Machine

This placement map contributes the repeated bit-slice layout, control route, and carry topology. Cartilage Core and its public source repository provide the current browser and hardware mechanism for installing and running Cartilage regions.