Cartilage Full-Adder Islands: Spatial MUX Arithmetic

A one-bit full adder becomes a readable spatial circuit when its parity, sum, and carry equations occupy distinct local MUX islands.

This 37x37 placement map brings B, A, and Cin through the top edge, connects them through wires, constants, intersections, and selectors, and delivers SUM and CARRY at the right edge.

The 2960x2960 image preserves the hand-drawn topology as a precise Cartilage design map with ten semantic labels and the complete full-adder equations.

Read The Complete 37x37 Placement Map

A 37 by 37 Cartilage placement map routing B, A, and Cin through local selector islands to right-edge SUM and CARRY signals — Three top-edge inputs feed local MUX islands; two right-edge routes carry the sum and carry results.

Follow One Bit Of Addition Through Space

The map exposes the arithmetic as a route: inputs enter from above, inversion and parity emerge in the first islands, Cin selects the sum, and the carry selector chooses between Cin and A.

The Cartilage Verified Ripple2 Adder runs this arithmetic pattern across two bits. Cartilage Core supplies the current browser and hardware mechanism; Cartilage 2026, the visual language, and the nested-instantiation mechanism connect the map to the larger fabric architecture.

Build The Full Adder From Five Local Selectors

Five MUX-friendly equations define the placed circuit:

notB  = B ? 0 : 1
P     = A ? notB : B
notP  = P ? 0 : 1
SUM   = Cin ? notP : P
CARRY = P ? Cin : A

MUX Algebra turns every conditional into one selector, so nested selectors implement the entire full-adder function with one local primitive.

P computes A xor B, SUM computes Cin xor P, and CARRY computes (A and B) or (Cin and (A xor B)).

Keep Runtime Data On Ordinary Fabric Routes

Neighboring wire cells carry the top-edge inputs and right-edge outputs as runtime data. Reconfiguration ports separately install or replace fabric roles.

The map therefore presents a configured arithmetic circuit: data enters through wire cells, crosses local MUX islands, and exits through wire cells while the configuration plane retains its own ports.

Use Space To Reveal Every Logic Island

A constant-zero sea separates the active islands, leaves room for labels, and makes each selector and route legible at full resolution.

Wire and intersection cells cut through that sea to carry B, A, Cin, P, SUM, and CARRY between islands and the fabric edge.

Carry The Hand-Drawn Topology Into Cartilage

The hand-drawn full-adder sheet establishes the spatial composition: B, A, and carry-in enter from the top, while SUM and carry-out leave to the right.

The published design map reconstructs that function with Cartilage constants, wires, intersections, and MUX roles.

Decode The Render At Full Resolution

The lattice contains 37x37 cells, and the PNG spans 2960x2960 pixels. Cycle-zero initialized roles form the circuit beneath ten semantic labels.

White boxes name signals for the reader. The Cartilage Visual Language decodes the 32-code cell-role alphabet beneath those callouts.

Extend The Island Pattern Into Running Arithmetic

This placement map contributes the local island notation and edge-routing plan. Cartilage Core and its public source repository provide the current browser and hardware mechanism, while the ripple2 page carries the arithmetic into a complete driven run.