This is a visual placement sketch for a one-bit full adder.

The intended full-adder mapping uses B, A, and Cin as top-edge data inputs, with SUM and CARRY routed to the right edge.

The useful part is still the mapping vocabulary: a familiar one-bit arithmetic block decomposed into local wire, constant, intersection, and MUX roles inside the same 32-code Cartilage visual language.

Visual placement sketchThis page is part of the Cartilage Run and Sketch Index.

Included: a 37x37 visual placement sketch, a 2960x2960 PNG, the intended full-adder equations, and the local MUX-island mapping vocabulary.

Sketch focus: local island notation, edge route intent, and the mapping from full-adder equations into Cartilage cell roles.

The Rendered Artifact

Cartilage fabric render of a full adder with B, A, and Cin entering from the top and SUM and CARRY leaving to the right — A 37x37 Cartilage visual placement sketch of an island-style full-adder instantiation.

What This Page Shows

The render shows the intended placement vocabulary for a full-adder island: top-edge input routes, local inversion and mux islands, and right-edge output routes.

For checked arithmetic behavior, use the Cartilage Verified Ripple2 Adder. For the current mechanism and hardware reference, use Cartilage Core; use Cartilage 2026, the visual language, and the nested-instantiation demo for the browser-artifact lineage.

The Boolean Function

The intended placed circuit is the extracted full-adder function, expressed as mux-friendly local equations:

notB  = B ? 0 : 1
P     = A ? notB : B
notP  = P ? 0 : 1
SUM   = Cin ? notP : P
CARRY = P ? Cin : A

Equivalently, P is A xor B, SUM is Cin xor P, and CARRY is (A and B) or (Cin and (A xor B)).

Data I/O Is Not Reconfiguration I/O

In the sketch, the top-edge inputs and right-edge outputs are ordinary data routes through neighboring fabric cells. They are not reconfiguration-port cells.

That distinction matters in Cartilage. Reconfiguration ports are for changing fabric state. This drawing is meant to show a configured arithmetic circuit: data entering over wire cells, flowing through local MUX islands, and exiting over wire cells.

Why The Islands Are Spread Out

The fabric is intentionally over-provisioned. Most cells remain in the constant-zero sea so the labels have readable space and each logic island can be inspected without the picture turning into a dense routing block.

The sea is interrupted by the wire cells and intersection cells needed to carry B, A, Cin, P, SUM, and CARRY between islands and to the fabric edge.

Relation To The Hand Sketch

The sketch is based on the hand-drawn full-adder sheet where B, A, and carry-in enter from the top and SUM plus carry-out leave to the right. It is not an OCR transcription of that photograph.

The published image is the extracted function mapped into available Cartilage cell roles: constants, wires, intersections, and MUX behavior.

Render Notes

The rendered lattice is 37x37 cells. The PNG is 2960x2960 pixels. It is a cycle-zero initialized-cell schematic with ten semantic labels.

Read the white label boxes as human callouts. The underlying fabric vocabulary is still the same Cartilage cell-role alphabet explained in the Cartilage Visual Language article.

Where It Fits

The useful part is the local island notation. Cartilage Core and its public source repository are the current mechanism and hardware reference. They do not turn this older cycle-zero placement sketch into a driven or verified circuit.