Model arithmetic on chips reduces quickly to concrete datapath and control pieces.

The post names the layer that matters for chip implementations: carry-save adders, parallel-prefix adders, one-hot state machines, H-trees, FIFO, clock-domain crossing, IEEE 754 FMA, bfloat16, and pipelined backpropagation when enough chip area is available.

Chip-arithmetic noteOriginally posted 2023-11-29; expanded here around datapath and control structures.

Article focus: carry-save adders, parallel-prefix adders, state-machine control, clock distribution, FIFO, CDC, FMA, bfloat16, and training datapaths.

The Datapath Pieces

AI arithmetic on chips eventually becomes a physical datapath. Carry-save adders reduce partial products without propagating every carry immediately. Parallel-prefix adders handle the carry-propagate step when the design needs a final binary result.

Multiply-accumulate and fused multiply-add units sit on top of those primitives, along with format choices such as IEEE 754 floating point, bfloat16, integer accumulators, and saturation or rounding behavior.

Control And Distribution

The arithmetic unit is not enough by itself. The chip also needs state-machine control, FIFOs, clock-domain crossings, reset strategy, clock distribution, power distribution, and physical routing that preserves timing.

That is why a simple arithmetic formula becomes a chip-design problem. The datapath, controller, clock tree, memory movement, and verification plan all have to agree.

Training On Large Chips

A fully pipelined training datapath is possible only when the chip has enough area and memory movement to keep forward values, gradient flow, parameter updates, and synchronization organized. The arithmetic primitive is visible, but the schedule and data placement decide whether the machine is usable.

The related bit-serial multiplier article takes the same idea at smaller scale: make the arithmetic schedule inspectable first, then ask how it composes into a larger fabric.