Original Post

When you fill up your entire largest FPGA, when you have to break away from one single chip package, when you have to partition your logic, and lower your clock ambition or redesign your latency expectations, work on SerDeses, pipelines, protocols, clock distribution networks, and time synchronization, often using GPS clock sources....

When you have to buy one more server rack, because you've used up all 2 kilowatts in their 36 units already....

When your engineers ask to use RISC-V, ARM, Intel, AMD, Nvidia, IBM, because they can't manage the complexity and dynamic models in their FPGAs... When they have to use Linux, Charm++, Kubernetes, parallel execution orchestration libraries and custom code on many levels of abstraction...

Simply, when you have to pay your talent for the duration of the project MUCH MORE than your entire hardware will cost with all its upgrades for the next 5 years....

That's where we need to talk. I'm a liberator who wants to save billions of engineering hours spent on custom FPGA coding, architecture, bugs, code from scratch over and over....

I want to help you to make your FPGA cluster deployments SCALE.

Because I know how to. Because I also know that nobody on Earth does know how to scale bare pure FPGAs without Linuxes glueing them. Without a complete redesign of a fixed-size server rack.

I know something that nobody else does, and I do want to help.