The original estimate used a fully pipelined FPGA chain: 100 devices over roughly 3 meters, clocked at 891 MHz, with an estimated traversal latency of about 0.113 milliseconds.

The useful question is whether cellular automata and mesh-style computation can use local timing and repeated structure instead of paying for wide global interconnect everywhere.

Hardware estimateOriginally posted 2021-06-04; expanded here around latency and topology.

Article focus: FPGA chains, cellular automata, mesh topology, pipelining, placement, and latency.

The Estimate

A fully pipelined chain changes how distance is paid for. The work does not wait for a combinational path across the whole fabric; each stage pays a clocked hop.

The 2021 estimate used 100 FPGAs over about 3 meters at 891 MHz and arrived at roughly 0.113 milliseconds for traversal through the chain. That is not a universal number. It is a scale check: local pipelined movement can be fast enough to deserve serious architectural attention.

Why Mesh Comes Back

Cellular automata are naturally local. Each cell reads a neighborhood, updates state, and lets the next step proceed from nearby information. That shape matches a mesh better than a design that assumes every stage needs a long-span wire or a global tree.

The engineering question is where the boundaries sit: FPGA-to-FPGA links, clock domains, placement, buffering, routing resources, and the update rule itself.

Tradeoff

A mesh does not remove architecture work. It moves the work into topology, pipeline depth, boundary latency, placement discipline, and programming model. That tradeoff is often preferable to hiding locality under a global communication pattern that becomes expensive at scale.