Cartilage Ripple2 Adder: 3,072 Updates, 96 Passing Expectations

A generated two-bit ripple-carry adder turns every pair of two-bit inputs into edge-visible sum and carry lanes inside the browser/GLSL Cartilage fabric.

The QFG netlist places 207 explicit wire, MUX, constant, and crossbar cells. Across 16 frame declarations and 3072 lockstep updates, the circuit computes {C2, S1, S0} = A[1:0] + B[1:0] and satisfies 96/96 browser expectations.

The full-resolution PNG, generated QFG source, and run report expose the same two-bit arithmetic from spatial layout through final readout.

See The Generated Two-Bit Datapath

A generated 32 by 32 Cartilage ripple-carry adder with two input words, sum lanes, carry routes, crossbars, and edge-visible results — A 32x32 fabric carries two input words through generated MUX islands, crossbars, sum lanes, and the ripple carry; the linked PNG spans 3072x3072 pixels.

Add All 16 Input Pairs

The adder consumes all 16 combinations of two two-bit words and exposes the three-bit result:

{C2, S1, S0} = A[1:0] + B[1:0]

The generated QFG places every primitive Cartilage cell directly. Its visible crossbars route intentional signal crossings inside the circuit.

Advance 3,072 Lockstep Fabric Updates

The browser/GLSL engine streams each QFG frame through the fabric and checks the arithmetic result at every frame transition:

207 explicit seed cells
16 parsed QFG frame declarations
3072 lockstep fabric updates
96 browser expectations checked
96 browser expectations passed

The QFG source defines the placed circuit, the report records all 96 passing expectations, and the image makes the generated routes readable at full resolution.

Read Three Result Bits At The Fabric Edge

Ordinary edge-visible lanes carry all three result bits:

S0 exits on the left edge at row 8
S1 exits on the right edge at row 16
C2 exits on the right edge at row 28

The final frame adds a=3, b=3 and produces binary 110. Active right-edge lanes 16 and 28 carry S1=1 and C2=1; the inactive left-edge lane at row 8 carries S0=0.

Open The Circuit And Its Complete Run Record

browser-static-ripple2-adder-edge.qfg contains the generated source netlist, and verification-report.md records the full run.

The screenshot turns those placed cells into a readable spatial circuit, while the source and report carry the exact frame declarations, expectations, and results.

Advance From Placement Maps To Generated Arithmetic

The full-adder islands and PC-stepper islands pages contribute spatial design maps. The three MUX lanes page contributes an edge-driven selector run. This ripple2 adder combines both strengths in one generated arithmetic circuit.

Generated source, a readable route map, edge-visible result lanes, and 96 passing expectations create a complete public path from circuit definition to browser execution.

Connect Four Views Of One Run

The QFG source defines the cells, the report records the frame-by-frame checks, the render exposes the routes, and the edge lanes display the arithmetic result from the same generated run.

Cartilage Core and the public source repository supply the current compact browser and hardware mechanism. This page’s QFG and run report supply the exact two-bit adder package.