This page gives the current public Cartilage arithmetic artifact: a generated 2-bit ripple-carry adder rendered in the browser/GLSL fabric and checked by the QFG verification run.

The circuit computes {C2, S1, S0} = A[1:0] + B[1:0]. The source is not a hand-drawn route sketch; it is a generated QFG primitive-cell netlist with concrete cells for wires, muxes, constants, and crossbars.

Verified arithmetic runThis page is part of the Cartilage Run and Sketch Index.

Included: 207 explicit seed cells, 16 parsed QFG frame declarations, 3072 lockstep fabric updates, and 96/96 browser expectations passed.

Run focus: one generated 2-bit adder run with its PNG, QFG source, verification report, and current Cartilage entry links.

The Rendered Artifact

Verified Cartilage 2-bit ripple-carry adder render with A and B input lanes, sum outputs, carry routes, verified crossbars, and edge surface labels — A 32x32 Cartilage fabric render of the verified 2-bit ripple-carry adder. The full-resolution 3072x3072 PNG is linked for inspection.

The Circuit

The adder consumes all 16 pairs of two-bit inputs and exposes the three-bit result:

{C2, S1, S0} = A[1:0] + B[1:0]

The generated QFG places the primitive Cartilage cells directly. The crossbars visible in the screenshot are intentional generated cells, not accidental overlay intersections.

The Verification Run

The browser/GLSL lockstep run streamed the QFG frames through the fabric and checked the result at frame boundaries:

207 explicit seed cells
16 parsed QFG frame declarations
3072 lockstep fabric updates
96 browser expectations checked
96 browser expectations passed

The run result is documented by the verification report and QFG source. The picture is the readable render of that generated fabric.

Output Surface

The result bits are routed to ordinary edge-visible readout lanes:

S0 exits on the left edge at row 8
S1 exits on the right edge at row 16
C2 exits on the right edge at row 28

The final checked frame is a=3, b=3, so the expected result is binary 110. The final edge readout has active right-edge lanes 16 and 28, matching S1=1 and C2=1; S0=0 is inactive.

Artifacts

The source netlist is available as browser-static-ripple2-adder-edge.qfg. The full verification report is available as verification-report.md.

The screenshot is a visualization of those artifacts. It is useful because it lets a reader follow the placed fabric, while verification comes from the generated QFG and the expectation checks.

What This Replaces

The previous full-adder islands, PC-stepper islands, and mux-lanes pages are now treated as draft or debug artifacts. The first two are visual placement sketches without edge-surface verification. The mux-lanes page is a useful debug fixture, but not the requested clean visitor-facing schematic.

This ripple2 adder is the current public replacement: generated source, readable render, edge-visible result lanes, and a passing browser expectation run.

Verification Boundary

The QFG source, verification report, rendered routes, and edge-visible result lanes should all describe the same generated 2-bit adder run.

Cartilage Core and the public source repository are the current compact mechanism and hardware reference. They are not the source tree for this QFG ripple-adder run; this page's QFG and verification report remain the evidence for the adder shown here.