Chip Capacity as DDoS-Style Distribution
December 8, 2021

Capacity noteOriginally posted 2021-12-08; rewritten here around distributed mature-node capability.

Included: regional capacity, mature CMOS, supply resilience, process capability, and why more centralized leading-edge capacity does not solve every chip shortage.

Article focus: chip capacity as infrastructure that should degrade gracefully instead of concentrating every dependency in a few places.

Capacity As Resilience

The DDoS analogy is useful because it separates peak performance from survivability. A network survives attack by having capacity, distribution, routing options, and graceful degradation. Chip supply has a similar problem when too many products depend on a small number of process locations.

Leading-edge fabs matter, but they are not the only capacity that matters. Many useful products need mature nodes, power devices, sensors, mixed-signal parts, packaging, test, and predictable availability more than the smallest transistor available.

Why Mature Nodes Matter

A regional 250 nm or similar mature process would not replace advanced logic. It could still support controllers, glue logic, educational chips, simple analog interfaces, industrial parts, and local repair or replacement paths.

The value is not glamour. The value is reducing single points of failure in the physical compute supply chain.

Useful Scope

This note does not propose that every town needs a complete leading-edge semiconductor ecosystem. It argues for distributed practical capability: process knowledge, equipment, inspection, packaging, and test near enough that the whole system does not fail when one remote queue closes.