Turing, Von Neumann, Boole, and Faggin
June 30, 2021

This note sketches a computing lineage: Boolean algebra, state, sequential circuits, VLSI, reconfigurable logic, and statistical workloads running on that substrate.

The useful point is not a hero ranking. It is that each layer gives the next layer a working handle: switching, memory, timing, layout, programmability, and large-scale execution.

Computing-history noteOriginally posted 2021-06-30; expanded here around the engineering sequence.

Article focus: Boolean algebra, sequential circuits, VLSI, FPGAs, statistical workloads, and Federico Faggin's Silicon.

The Engineering Line

The technical thread runs from Boolean operations to stateful switching networks. Boolean algebra gives the logic. Sequential circuits add memory and timing. Circuit minimization, state machines, and switching theory make the structure implementable.

Faggin's Intel 4004 belongs to the VLSI step: sequential Boolean circuits became a manufactured processor with layout, timing, and control discipline. Freeman's FPGA direction added another layer: a manufactured fabric that can be configured into many circuits after fabrication.

Why The Sequence Matters

Machine-learning workloads do not float above this history. They run on switching hardware, memory systems, arithmetic units, interconnect, and software stacks built on earlier layers. The name "AI" should not hide the substrate that makes the workload execute.

The same point applies to programmable fabrics. An FPGA is useful because it turns a fixed chip into a surface for many hardware schedules. That makes the boundary between program, circuit, placement, and timing unusually visible.

Source Context

The original post linked Federico Faggin's Silicon. The book is kept here as source context for the VLSI and microprocessor thread, not as a complete history of computation.

Federico Faggin, Silicon

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