# From one decision to a received program

## Threshold observations

Write the comparator observation as b[n]=1{v_RF[n]>θ[n]} after choosing
polarity, and x[n]=2b[n]−1. The physical wiring in this build has the useful
control polarity that increasing the pin 4 capacitor voltage increases the
reported fraction of ones. Threshold-crossing time carries frequency and
phase. Accumulating many decisions also carries threshold-dependent amplitude
information.

For an ideal sine GA cos(φ), uniform phase coverage, and a fixed threshold
within the sine's excursion:

    D = arccos(θ/(GA))/π
    A = θ / [G cos(πD)]

This is the single-tone transfer relation, not a formula for separating an
arbitrary mixture of stations. Gain, offset, noise, hysteresis and the physical
input transfer belong in the calibration model. At θ=0 the ideal duty fraction
is 1/2 regardless of A. A known nonzero threshold creates amplitude sensitivity.

## Quadrature and two translations

At nominal 408M decisions/s, fixed alternating sign/permutation patterns form
quadrature around 102 MHz. The J1 path integrates matched groups of 16 RF decisions
before the second mixers. Its 49-bit DDS advances at 25.5 MHz. For the included
106.5 MHz image:

    M = round((106.5 MHz −102 MHz) ×2^49 /25.5 MHz)
      =99,344,109,427,290

The top two phase bits supply the square-wave quadrature signs. The sign
signals pass through registered duplication trees. Let A and B denote the
integrated quadrature words, and C and S the DDS-controlled±1 signs. The
implemented four products and recombination are:

    II=A·C, QQ=B·S, IQ=A·S, QI=B·C
    I_out=QQ−II
    Q_out=IQ+QI

Do not replace the four products by unrelated XORs or swap one sign without
tracking the lane convention. The source's ordering and delay alignment define
the selected sideband. The filters between the two translations are part of
the receiver, not optional postprocessing. Square-wave harmonic responses
remain distinct from the image cancellation supplied by quadrature.

## Continuous integration and selected-channel decimation

The J1 tap uses three nonresetting integrators followed by decimation 64 and
three delayed differences. In ideal linear arithmetic its normalized response is

    H(z) = [(1−z^(−64))/(64(1−z^(−1)))]^3
    f_IQ =25.5 MHz/64 =398,437.5 complex samples/s

Modulo arithmetic preserves the intended fixed-width differences. Carry-save
compressors, four-bit terminal resolvers and pipelined/serial stages implement
the arithmetic rather than inferred wide parallel additions or DSP blocks.
The image retains signed 32-bit I and Q values. Word width describes the numeric
representation; conversion to calibrated RF amplitude requires the threshold
transfer model.

The wideband image is a separate acquisition mode. It preserves the entire
408M-decision/s comparator stream, and its F2 path uses matched four-decision
sliding integration with stride 2 before its second mixer. The J1 channel
decimator does not replace or truncate the full-band raw recording.

## Host FM and the published audio

With z[n]=I[n]+jQ[n], the phase-difference discriminator is

    f[n] = f_IQ/(2π) · arg(z[n] · conjugate(z[n−1]))

The host removes the record's mean frequency offset, applies a fourth-order
15 kHz Butterworth low-pass and 75µs de-emphasis, and resamples to 48 kHz mono.
The listening file uses one constant gain over the whole record. There is no
audio SDM on the FPGA output, no repeated audio and no gap filling. The release
also contains the exact second-order tracking-FM alternative and fixed-gain
phase/tracking files generated by replay. Listening and tracking are distinct
outputs; the published audio is the phase-difference path.

## FPGA-only bias feedback

The controller counts all comparator observations using a rolling 4096-bit
window updated every 1024 decisions. If S is a nonresetting cumulative sum,

    d[k] = S[k]−S[k−4096]
    D[k] = d[k]/4096

The physical polarity calls for sinking when density is high. Profile 5's
hysteresis thresholds are 2944 and 3200 counts, or 71.875% and 78.125%, around 75%.
Its state equation is:

    above upper threshold: request sinking
    below lower threshold: stop requesting sinking
    between thresholds: keep the previous request

The pulse scheduler permits only one processing-clock low pulse every 128
clocks, and only after warmup and an explicit arm. Weak charging provides the
opposite direction. ADC measurements established the actuation polarity; the
ADC is not an input to the running controller. The selected operating point
comes from reception, rather than assuming 50% is always the best audio point.

The implementation is in `gf_bias_servo` and the shared compressor/resolver
modules. Exact source, timing summaries and the recording input CRC are in
the release, so every numerical stage can be followed back to its decisions.